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Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET
DS3105
Line Card Timing IC
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing cards. The DS3105 continually monitors both inputs and performs automatic hitless reference switching if the primary reference fails. The highly programmable DS3105 supports numerous input and output frequencies including frequencies required for SONET/SDH, Synchronous Ethernet (1G, 10G and 100Mb/s), wireless basestations and CMTS systems. PLL bandwidths from 18 Hz to 400 Hz are supported, and a wide variety of PLL characteristics and device features can be configured to meet the needs of many different applications. The DS3105 register set is backward compatible with Semtech's ACS8525 line card timing IC. The DS3105 pinout is similar but not identical to the ACS8525.
FEATURES
Advanced DPLL Technology Programmable PLL bandwidth: 18 Hz to 400 Hz Hitless Reference Switching, Automatic or Manual Holdover on Loss of All Input References Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless and CMTS Rates 5 Input Clocks Two CMOS/TTL (125 MHz) Two LVDS/LVPECL/CMOS/TTL (156.25 MHz) Backup Input (CMOS/TLL) in Case of Complete Loss of System Timing References Three Optional Frame Sync Inputs (CMOS/TTL) Continuous Input Clock Quality Monitoring Numerous Input Clock Frequencies Supported - SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz - Ethernet xMII: 2.5, 25, 125, 156.25 MHz - PDH: N x DS1, N x E1, N x DS2, DS3, E3 - Frame Sync: 2 kHz, 4 kHz, 8 kHz - Custom: Any Multiple of 2 kHz up to 131.072 MHz,
Any Multiple of 8 kHz up to 155.52 MHz
APPLICATIONS
SONET/SDH, Synchronous Ethernet, PDH and Other Line Cards in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations.
FUNCTIONAL DIAGRAM
LVDS/LVPECL or CMOS/TTL
IC3 IC4 IC5 IC6 IC9
OC3
2 Output Clocks One CMOS/TTL Output (125 MHz) One LVDS/LVPECL Output (312.50 MHz) Two Optional Frame Sync Outputs: 2 kHz, 8 kHz Numerous Output Clock Frequencies Supported - SONET/SDH: 6.48, N x 19.44, N x 51.84 MHz - Ethernet xMII: 2.5, 25, 125, 156.25, 312.5 MHz - PDH: N x DS1, N x E1, N x DS2, DS3, E3 - Other: 10, 10.24, 13, 30.72 MHz, plus other frequencies available upon request - Frame Sync: 2 kHz, 8 kHz
- Custom Clock Rates: Any Multiple of 2 kHz up to 77.76 MHz, Any Multiple of 8 kHz up to 311.04 MHz
DS3105
OC6 LVDS/LVPECL
SYNC1 SYNC2 SYNC3 local oscillator
FSYNC MFSYNC
General Suitable line card IC for stratum 3E/3/4, SMC, SEC Internal Compensation for Master Clock Oscillator SPI Processor Interface 1.8V Operation with 3.3V I/O (5V tolerant) Industrial Operating Temperature Range
control status
ORDERING INFORMATION
PART DS3105LN DS3105LN+ TEMP RANGE -40 to 85C -40 to 85C PACKAGE LQFP64 LQFP64, RoHS compliant
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REV: 061507
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DS3105
TABLE OF CONTENTS
1 2 3 4 5 6 7 STANDARDS COMPLIANCE ............................................................................................................................... 6 APPLICATION EXAMPLE..................................................................................................................................... 7 BLOCK DIAGRAM ................................................................................................................................................ 7 DETAILED DESCRIPTION ................................................................................................................................... 8 DETAILED FEATURES......................................................................................................................................... 9 PIN DESCRIPTIONS .......................................................................................................................................... 11 FUNCTIONAL DESCRIPTION............................................................................................................................ 15 7.1 7.2 7.3 7.4 Overview.................................................................................................................................................... 15 Device Identification and Protection .......................................................................................................... 16 Local Oscillator and Master Clock Configuration ...................................................................................... 16 Input Clock Configuration .......................................................................................................................... 16 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.7.8 7.7.9 Signal Format Configuration......................................................................................................... 16 Frequency Configuration .............................................................................................................. 17 Frequency Monitoring................................................................................................................... 18 Activity Monitoring ........................................................................................................................ 18 Selected Reference Activity Monitoring........................................................................................ 19 Priority Configuration .................................................................................................................... 20 Automatic Selection Algorithm ..................................................................................................... 20 Forced Selection........................................................................................................................... 21 Ultra-Fast Reference Switching.................................................................................................... 21 External Reference Switching Mode ............................................................................................ 21 Output Clock Phase Continuity During Reference Switching....................................................... 21 T0 DPLL State Machine ............................................................................................................... 23 T4 DPLL State Machine ............................................................................................................... 26 Bandwidth..................................................................................................................................... 26 Damping Factor ............................................................................................................................ 26 Phase Detectors ........................................................................................................................... 26 Loss of Phase Lock Detection...................................................................................................... 27 Phase Build-Out ........................................................................................................................... 28 Input to Output (Manual) Phase Adjustment ................................................................................ 28 Phase Recalibration ..................................................................................................................... 28
Input Clock Monitoring............................................................................................................................... 18
Input Clock Priority, Selection and Switching ............................................................................................ 20
DPLL Architecture and Configuration........................................................................................................ 22
7.7.10 Frequency and Phase Measurement ........................................................................................... 29 7.7.11 Input Jitter Tolerance.................................................................................................................... 30 7.7.12 Jitter Transfer ............................................................................................................................... 30 7.7.13 Output Jitter and Wander ............................................................................................................. 30
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DS3105
Output Clock Configuration ....................................................................................................................... 31 7.8.1 7.8.2 Signal Format Configuration......................................................................................................... 31 Frequency Configuration .............................................................................................................. 31 Sampling....................................................................................................................................... 38 Resampling................................................................................................................................... 39 Enable .......................................................................................................................................... 39 Qualification.................................................................................................................................. 39 Output Clock Alignment................................................................................................................ 39 Frame Sync Monitor ..................................................................................................................... 39 SYNCn Pins.................................................................................................................................. 40 Other Configuration Options......................................................................................................... 40
7.9
Frame and Multiframe Alignment .............................................................................................................. 38 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.9.7 7.9.8
7.10 Microprocessor Interface ........................................................................................................................... 41 7.11 Reset Logic................................................................................................................................................ 43 7.12 Power-Supply Considerations ................................................................................................................... 43 7.13 Initialization................................................................................................................................................ 43 8 REGISTER DESCRIPTIONS.............................................................................................................................. 44 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.4 Status Bits ................................................................................................................................................. 44 Configuration Fields................................................................................................................................... 44 Multi-Register Fields.................................................................................................................................. 44 Register Definitions ................................................................................................................................... 45 JTAG Description ...................................................................................................................................... 93 JTAG TAP Controller State Machine Description ..................................................................................... 93 JTAG Instruction Register and Instructions............................................................................................... 95 JTAG Test Registers ................................................................................................................................. 96
JTAG TEST ACCESS PORT AND BOUNDARY SCAN..................................................................................... 93
10 ELECTRICAL CHARACTERISTICS ................................................................................................................... 97 10.1 DC Characteristics..................................................................................................................................... 97 10.2 Input Clock Timing................................................................................................................................... 100 10.3 Output Clock Timing ................................................................................................................................ 100 10.4 SPI Interface Timing ................................................................................................................................ 101 10.5 JTAG Interface Timing............................................................................................................................. 102 10.6 Reset Pin Timing ..................................................................................................................................... 103 11 PIN ASSIGNMENTS ......................................................................................................................................... 104 12 MECHANICAL INFORMATION ........................................................................................................................ 106 13 ACRONYMS AND ABBREVIATIONS............................................................................................................... 108 14 DATA SHEET REVISION HISTORY ................................................................................................................ 109
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DS3105
LIST OF FIGURES
Figure 2-1. Typical Application Example ..................................................................................................................... 7 Figure 3-1. Functional Block Diagram ......................................................................................................................... 7 Figure 7-1. DPLL Block Diagram ............................................................................................................................... 22 Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 24 Figure 7-3. FSYNC 8 kHz Options............................................................................................................................. 38 Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 42 Figure 7-5. SPI Bus Transactions.............................................................................................................................. 42 Figure 9-1. JTAG Block Diagram............................................................................................................................... 93 Figure 9-2. JTAG TAP Controller State Machine ...................................................................................................... 95 Figure 10-1. Recommended Termination for LVDS Pins .......................................................................................... 99 Figure 10-2. Recommended Termination for LVPECL Signals on Differential Input Pins ........................................ 99 Figure 10-3 Recommended Termination for LVPECL Level-Compatible Output Pins.............................................. 99 Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 101 Figure 10-5. JTAG Timing Diagram......................................................................................................................... 102 Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 103 Figure 11-1. Pin Assignment Diagram..................................................................................................................... 105 Figure 12-1. LQFP Mechanical Dimensions............................................................................................................ 106
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LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 11 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 11 Table 6-3. Global Pin Descriptions ............................................................................................................................ 12 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 13 Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 13 Table 6-6. Power Supply Pin Descriptions ................................................................................................................ 13 Table 7-1. Input Clock Capabilities ............................................................................................................................ 17 Table 7-2. Locking Frequency Modes ....................................................................................................................... 17 Table 7-3. Default Input Clock Priorities .................................................................................................................... 20 Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 26 Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 30 Table 7-6. Output Clock Capabilities ......................................................................................................................... 31 Table 7-7. Digital1 Frequencies................................................................................................................................. 32 Table 7-8. Digital2 Frequencies................................................................................................................................. 33 Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 33 Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 33 Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 33 Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 34 Table 7-13. OC3 and OC6 Output Frequency Selection ........................................................................................... 34 Table 7-14. Possible Frequencies for Programmable Outputs ................................................................................. 35 Table 7-15 T0CR1.T0FREQ Default Settings ........................................................................................................... 37 Table 7-16 T4CR1.T4FREQ Default Settings ........................................................................................................... 37 Table 7-17 OC6 Default Frequency Configuration .................................................................................................... 37 Table 7-18 OC3 Default Frequency Configuration .................................................................................................... 37 Table 7-19. External Frame Sync Source ................................................................................................................. 40 Table 8-1. Register Map ............................................................................................................................................ 45 Table 9-1. JTAG Instruction Codes ........................................................................................................................... 95 Table 9-2. JTAG ID Code .......................................................................................................................................... 96 Table 10-1. Recommended DC Operating Conditions .............................................................................................. 97 Table 10-2. DC Characteristics.................................................................................................................................. 97 Table 10-3. CMOS/TTL Pins ..................................................................................................................................... 98 Table 10-4. LVDS/LVPECL Input Pins ...................................................................................................................... 98 Table 10-5. LVDS Output Pins .................................................................................................................................. 98 Table 10-6. LVPECL Level-Compatible Output Pins................................................................................................. 98 Table 10-7. Input Clock Timing................................................................................................................................ 100 Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 100 Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode............................................................ 100 Table 10-10. SPI Interface Timing ........................................................................................................................... 101 Table 10-11. JTAG Interface Timing........................................................................................................................ 102 Table 10-12. Reset Pin Timing ................................................................................................................................ 103 Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 104 Table 12-1. LQFP Thermal Properties, Natural Convection.................................................................................... 107 Table 12-2. LQFP Theta-JA (JA) vs. Airflow ........................................................................................................... 107
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1 STANDARDS COMPLIANCE
Table 1-1. Applicable Telecom Standards
SPECIFICATION ANSI T1.101 TIA/EIA-644-A ETSI EN 300 417-6-1 EN 300 462-3-1 EN 300 462-5-1 IEEE IEEE 1149.1 ITU-T G.783 G.813 G.823 G.824 G.825 G.8261 G.8262 TELCORDIA GR-253-CORE GR-1244-CORE SPECIFICATION TITLE Synchronization Interface Standard, 1999 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 Transmission and Multiplexing (TM); Generic Requirements of Transport Functionality of Equipment; Part 6-1: Synchronization Layer Functions, v1.1.3 (1999-05) Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks; Part 3-1: The Control of Jitter and Wander within Synchronization Networks, v1.1.1 (1998-05) Transmission and Multiplexing (TM); Generic Requirements for Synchronization Networks; Part 5-1: Timing Characteristics of Slave Clocks Suitable for Operation in Synchronous Digital Hierarchy (SDH) Equipment, v1.1.1 (1998-05) Standard Test Access Port and Boundary-Scan Architecture, 1990 ITU G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks (10/2000 plus Amendment 1 06/2002 and Corrigendum 2 03/2003) Timing characteristics of SDH equipment slave clocks (SEC) (03/2003) The Control of Jitter and Wander within Digital Networks which are Based on the 2048kbps Hierarchy (03/2000) The Control of Jitter and Wander within Digital Networks which are Based on the 1544kbps Hierarchy (03/2000) The Control of Jitter and Wander within Digital Networks which are Based on the Synchronous Digital Hierarchy (SDH) (03/2000) Timing and Synchronization Aspects in Packet Networks (05/2006) Timing characteristics of Synchronous Ethernet Equipment slave clock (EEC) (06/2007, pre-published) SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000 Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000
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2 APPLICATION EXAMPLE
Figure 2-1. Typical Application Example
prog. bandwidth, phase build-out, holdover, etc.
DS3105
From Master Timing Card From Slave Timing Card 19.44 MHz 19.44 MHz IC3 IC4 Input Clock Selector, Divider, Monitor Output Clock Synthesizer and Selector 19.44 MHz OC3 OC6 155.52MHz differential To SONET/SDH framers, Clock Multiplying APLLs, etc. on the Line Card
T0 DPLL
XO or TCXO
3 BLOCK DIAGRAM
Figure 3-1. Functional Block Diagram
T4 DPLL
IC3 IC4 IC5 POS/NEG IC6 POS/NEG IC9 (phase/freq. measurement)
SYNC1 SYNC2 SYNC3/ O3F0
Input Clock Selector, Divider and Monitor
PLL Bypass
T0 DPLL
(Filtering, Holdover, Hitless Switching, Frequency Conversion)
Output Clock Synthesizer and Selector
(Muxes, 7 DFS Blocks, 3 APLLs, Output Dividers)
OC3 OC6 POS/NEG FSYNC MFSYNC
JTRST* JTMS JTCLK JTDI JTDO
JTAG
Microprocessor Port
(SPI Serial) and HW Control and Status Pins
Master Clock Generator
CPHA CS SCLK SDI SDO
INTREQ / SRFAIL SRCSW SONSDH / GPIO4 O6F[2:0] / GPIO[3:1] O3F[1] / SRFAIL O3F[2] / LOCK
RST* TEST
REFCLK
Local Oscillator
See Figure 7-1 on page 22 for a detailed view of the T0 and T4 DPLLs and the Output Clock Synthesizer and Selector block.
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4 DETAILED DESCRIPTION
Figure 3-1 illustrates the blocks described in this section and how they relate to one another. Section 5 provides a detailed feature list. The DS3105 is a complete line card timing IC. At the core of this device are two digital phase-locked loops (DPLLs) labeled T0 and T4 1. DPLL technology makes uses of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to implement PLLs that are precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process variations. The DS3105's DPLLs are digitally configurable for input and output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. Both DPLLs can directly lock to many common telecom frequencies and also can lock at 8 kHz to any multiple of 8 kHz up to 156.25 MHz. The DPLLs can also tolerate and filter significant amounts of jitter and wander. In typical line card applications, the T0 DPLL takes reference clock signals from two redundant system timing cards, monitors both, selects one, and uses that reference to produce a variety of clocks that are needed to time the outgoing traffic interfaces of the line card (SONET/SDH, PDH, Synchronous Ethernet, etc.). To perform this role in a variety of systems with diverse performance requirements, the T0 DPLL has a sophisticated feature set and is highly configurable. T0 can automatically transition among free-run, locked and holdover states without software intervention. In free-run, T0 generates a stable, low-noise clock with the same frequency accuracy as the external oscillator connected to the REFCLK pin. With software calibration the DS3105 can even improve the accuracy to within 0.02 ppm. When at least one input reference clock has been validated, T0 transitions to the locked state in which its output clock accuracy is equal to the accuracy of the input reference. While in the locked state, T0 acquires an average frequency value to use as the holdover frequency. When its selected reference fails, T0 can very quickly detect the failure and enter the holdover state to avoid affecting its output clock. From holdover it can automatically switch to another input reference, again without affecting its output clock (hitless switching). Switching among input references can be either revertive or nonrevertive. When all input references are lost, T0 stays in holdover in which it generates a stable low-noise clock with initial frequency accuracy equal to its stored holdover value and drift performance determined by the quality of the external oscillator. T0 can also perform phase build-outs and fine-granularity output clock phase adjustments. In the DS3105 the T4 DPLL can only be used as an optional clock monitoring block. T4 can be directed to lock to an input clock and can measure the frequency of the input clock or the phase difference between two input clocks. At the front end of the T0 DPLL is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This block continuously monitors as many as 5 different input clocks of various frequencies for activity and coarse frequency accuracy. In addition, ICSDM maintains an input clock priority table for the T0 DPLL and can automatically select and provide the highest priority valid clock to T0 without any software intervention. The ICSDM block can also divide the selected clock down to a lower rate as needed by the DPLL. The Output Clock Synthesizer and Selector (OCSS) block shown in Figure 3-1 and in more detail in Figure 7-1 contains three output APLLs--T0 APLL, T0 APLL2 and T4 APLL--and their associated DFS engines and output divider logic plus several additional DFS engines. The APLL DFS blocks do frequency translation, creating clocks of various frequencies that are phase/frequency locked to the output clock of the associated DPLL. The APLLs multiply the clock rates from the APLL DFS blocks and simultaneously attenuate jitter. Altogether the output blocks of the DS3105 can produce more than 90 different output frequencies including common SONET/SDH, PDH and Synchronous Ethernet rates plus 2 kHz and 8 kHz frame sync pulses. Note that in the DS3105 the T4 APLL and its DFS engine are hardwired to the T0 DPLL and cannot be connected to the T4 DPLL. The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus the free-run and holdover stability of the DS3105 is entirely a function of the stability of the external oscillator, the performance of which can be selected to match the application: typically XO or TCXO. The 12.8MHz clock from the external oscillator is multiplied by 16 by the Master Clock Generator block to create the 204.8MHz master clock used by the rest of the device.
1
These names are adapted from output ports of the SETS function specified in ITU and ETSI standards such as ETSI EN 300 462-2-1. Although strictly speaking these names are appropriate only for timing card ICs such as the DS3100 that can serve as the SETS function, the names have been carried over to the DS3105 so that all of the products in Dallas/Maxim's timing IC product line have consistent nomenclature. Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
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5 DETAILED FEATURES
Input Clock Features
* * * * * * Five input clocks: Three CMOS/TTL (125 MHz) and two LVDS/LVPECL/CMOS/TTL (156.25 MHz) CMOS/TTL Input clocks accept any multiple of 2kHz up to 125MHz LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25 MHz All input clocks are constantly monitored by programmable activity monitors Fast activity monitor can disqualify the selected reference after two missing clock cycles Three optional 2/4/8 kHz frame sync inputs for frame sync signals from master and slave timing cards and an optional backup timing source
* * * * * * * * * * * * * * * *
T0 DPLL Features
High-resolution DPLL plus three low-jitter output APLLs Sophisticated state machine automatically transitions between free-run, locked and holdover states Revertive or non-revertive reference selection algorithm Programmable bandwidth from 18 Hz to 400 Hz Separately configurable acquisition bandwidth and locked bandwidth Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 Multiple phase detectors: phase/frequency, early/late, and multi-cycle Phase/frequency locking (360 capture) or nearest-edge phase locking (180 capture) Multi-cycle phase detection and locking (up to 8191 UI) improves jitter tolerance and lock time Phase build-out in response to reference switching Less than 5 ns output clock phase transient during phase build-out Output phase adjustment up to 200 ns in 6 ps steps with respect to selected input reference High-resolution frequency and phase measurement Holdover frequency averaging over 1 second interval Fast detection of input clock failure and transition to holdover mode Low-jitter frame sync (8 kHz) and multi-frame sync (2 kHz) aligned with output clocks
* * * * * * * *
T4 DPLL Features
High-resolution DPLL can be used to monitor inputs Programmable bandwidth from 18 Hz to 70 Hz Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10 or 20 Multiple phase detectors: phase/frequency, early/late, and multi-cycle Phase/frequency locking (360 capture) or nearest-edge phase locking (180 capture) Multi-cycle phase detection and locking (up to 8191 UI) improves jitter tolerance and lock time Phase detector can be used to measure phase difference between two input clocks High-resolution frequency and phase measurement
Output APLL Features
* * * * Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates, Fast/Gigabit Ethernet rates and 10G Ethernet rates, all locked to a common reference clock The T0 APLL, has frequency options suitable for Nx19.44MHz, NxDS1, NxE1, Nx25MHz and Nx62.5MHz The T4 APLL has frequency options suitable for Nx19.44MHz, NxDS1, NxE1, NxDS2, DS3, E3, Nx10MHz, Nx10.24 MHz, Nx13MHz, Nx25 MHz and Nx62.5 MHz The T0 APLL2 produces 312.5 MHz for 10G Synchronous Ethernet applications
Output Clock Features
* * Two output clocks: one CMOS/TTL (125 MHz) and one LVDS/LVPECL (312.50 MHz) Output clock rates include 2 kHz, 8 kHz, NxDS1, NxE1, DS2, DS3, E3, 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 2.5 MHz, 25 MHz, 125 MHz, 156.25 MHz, 312.50 MHz, 10 MHz, 10.24 MHz, 13 MHz, 30.72 MHz and various multiples and submultiples of these rates
Custom clock rates also available: any multiple of 2 kHz up to 77.76 MHz and any multiple of 8 kHz up to 311.04MHz
* *
All outputs have < 1 ns peak-to-peak output jitter; outputs from APLLs have < 0.5 ns peak-to-peak
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8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can be disciplined by a 2 kHz or 8 kHz sync input
General Features
* * * * Operates from a single external 12.800 MHz local oscillator (XO or TCXO) SPI serial microprocessor interface Four general-purpose I/O pins Register set can be write-protected
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6 PIN DESCRIPTIONS
Table 6-1. Input Clock Pin Descriptions
Pin Name(1)
REFCLK IC3 IC4
Type(2)
I IPD IPD
Pin Description
Reference Clock. Connect to a 12.800 MHz, high-accuracy, high-stability, low-noise local oscillator (XO or TCXO). See section 7.3. Input Clock 3. CMOS/TTL. Programmable frequency (default 8 kHz). This input can be associated with the SYNC1 pin. Input Clock 4. CMOS/TTL. Programmable frequency (default 8 kHz). This input can be associated with the SYNC2 pin. Input Clock 5. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz). LVDS/LVPECL: see Table 10-4, Figure 10-1 and Figure 10-2. CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS. This input can be associated with the SYNC1 pin. Input Clock 6. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz). LVDS/LVPECL: see Table 10-4, Figure 10-1 and Figure 10-2. CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS. This input can be associated with the SYNC2 pin. Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44 MHz). This input can be associated with the SYNC3 pin. Frame Sync1 Input. 2 kHz, 4 kHz or 8 kHz. FSCR3:SOURCE != 11XX This pin is the external frame sync input associated with any input pin using the FSCR3:SOURCE field. FSCR3:SOURCE = 11XX This pin is the external frame sync signal associated with IC3 or IC5 depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Frame Sync2 Input. 2 kHz, 4 kHz or 8 kHz. FSCR3:SOURCE != 11XX This pin is not used for the external frame sync signal. FSCR3:SOURCE = 11XX This pin is the external frame sync signal associated with IC4 or IC6 depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Frame Sync3 Input. 2 kHz, 4 kHz or 8 kHz. / OC3 Frequency Select 0. This pin is sampled when the RST pin goes high and the value is used as O3F0 which together with O3F2 and O3F1 sets the default frequency of the OC3 output clock pin. See Table 7-18. After RST goes high this pin becomes the SYNC3 input pin (2, 4 or 8 kHz) associated with IC9. It is only used as SYNC3 when FSCR2.SOURCE = 11XX.
IC5POS, IC5NEG
IDIFF
IC6POS, IC6NEG
IDIFF
IC9
IPD
SYNC1
IPD
SYNC2
IPD
SYNC3 / O3F0
IPU
Table 6-2. Output Clock Pin Descriptions
Pin Name(1)
OC3 OC6POS, OC6NEG FSYNC MFSYNC
Type(2)
O
Pin Description
Output Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by O3F[2:0] pins when the RST pin goes high, 19.44 MHz if O3F[2:0] pins left open). See Table 7-18. Output Clock 6. LVDS/LVPECL. Programmable frequency. Default frequency selected by O6F[2:0] pins when the RST pin goes high, 38.88 MHz if O6F[2:0] pins left open). The output mode is selected by MCR8.OC6SF[1:0]. See Table 10-5, Table 10-6 , Figure 10-1 and Figure 10-3. 8 kHz FSYNC. CMOS/TTL. 8 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse polarity and width are selectable using FSCR1.8KINV and FSCR1.8KPUL. 2 kHz MFSYNC. CMOS/TTL. 2 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse polarity and width are selectable using FSCR1.2KINV and FSCR1.2KPUL.
ODIFF
O3 O3
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Table 6-3. Global Pin Descriptions
Pin Name(1)
RST
Type(2) IPU
Pin Description
Reset (active low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as RST is low. RST should be held low for at least two REFCLK cycles after the external oscillator has stabilized and is providing valid clock signals. Source Switching Fast source-switching control input. See section 7.6.5. The value of this pin is latched into MCR10:EXTSW when RST goes high. After RST goes high this pin can be used to select between IC3/IC5 and IC4/IC6, if enabled. Factory Test Mode Select. Wire this pin to VSS for normal operation. OC3 Frequency Select 1 / SRFAIL Status Pin . This pin is sampled when the RST pin goes high and the value is used as O3F1 which together with O3F2 and O3F0 sets the default frequency of the OC3 output clock pin. See Table 7-18. After RST goes high, if MCR10:SRFPIN = 1, this pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the system a very fast indication of the failure of the current reference. When MCR10:SRFPIN = 0, SRFAIL is disabled (low). OC3 Frequency Select 2 / T0 DPLL LOCK Status /. This pin is sampled when the RST pin goes high and the value is used as O3F2 which together with O3F1 and O3F0 sets the default frequency of the OC3 output clock pin. See Table 7-18. After RST goes high, if MCR1.LOCKPIN=1, this pin indicates the lock state of the T0 DPLL. When MCR1.LOCKPIN=0, LOCK is disabled (low). 0 = Not Locked 1 = Locked OC6 Frequency Select 0 / General Purpose I/O Pin 1. This pin is sampled when the RST pin goes high and the value is used as O6F0 which together with O6F2 and O6F1 sets the default frequency of the OC6 output clock pin. See Table 7-17. After RST goes high this pin can be used as a general purpose I/O pin. GPCR:GPIO1D configures this pin as an input or an output. GPCR:GPIO1O specifies the output value. GPSR:GPIO1 indicates the state of the pin. OC6 Frequency Select 1 / General Purpose I/O Pin 2. This pin is sampled when the RST pin goes high and the value is used as O6F1 which together with O6F2 and O6F0 sets the default frequency of the OC6 output clock pin. See Table 7-17. After RST goes high this pin can be used as a general purpose I/O pin. GPCR:GPIO2D configures this pin as an input or an output. GPCR:GPIO2O specifies the output value. GPSR:GPIO2 indicates the state of the pin. OC6 Frequency Select 2 / General Purpose I/O Pin 3. This pin is sampled when the RST pin goes high and the value is used as O6F2 which together with O6F1 and O6F0 sets the default frequency of the OC6 output clock pin. See Table 7-17. After RST goes high this pin can be used as a general purpose I/O pin. GPCR:GPIO3D configures this pin as an input or an output. GPCR:GPIO3O specifies the output value. GPSR:GPIO3 indicates the state of the pin. SONET/SDH Frequency Select Input or GPIO4 Pin. When RST goes high the state of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS and MCR6:DIG2SS. After RST goes high this pin can be used as a general purpose I/O pin. GPCR:GPIO4D configures this pin as an input or an output. GPCR:GPIO4O specifies the output value. GPSR:GPIO4 indicates the state of the pin. Reset latched values: 0 = SDH rates (N x 2.048 MHz) 1 = SONET rates (N x 1.544 MHz) Interrupt Request / Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit determines whether the pin is indicates interrupt requests or loss of signal (i.e. loss of selected reference). INTCR:LOS=0: INTREQ mode The behavior of this pin is configured in the INTCR register. Polarity can be active-high or active-low. Drive action can be push-pull or open-drain. The pin can also be configured as a general-purpose output if the interrupt request function is not needed. INTCR:LOS=1: LOS mode This pin indicates the real-time state of the selected reference activity monitor (see section 7.5.3). This function is most useful when external switching mode (section 7.6.5) is enabled (MCR10:EXTSW=1).
SRCSW TEST
IPD IPD IOPU
O3F1 / SRFAIL
O3F2 / LOCK
IOPD
O6F0 / GPIO1
IOPD
O6F1 / GPIO2
IOPD
O6F2 / GPIO3
IOPU
SONSDH / GPIO4
IOPD
INTREQ / LOS
O3
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Table 6-4. SPI Bus Mode Pin Descriptions
See section 7.10 for functional description and section 10.4 for timing specifications.
Pin Name(1)
CS SCLK SDI SDO CPHA
Type(2)
IPU I I O I
Pin Description
Chip Select. This pin must be asserted (low) to read or write internal registers. Serial Clock. SCLK is always driven by the SPI bus master. Serial Data Input. The SPI bus master transmits data to the device on this pin. Serial Data Output. The device transmits data to the SPI bus master on this pin. Clock Phase See Figure 7-4. 0 = data is latched on the leading edge of the SCLK pulse 1 = data is latched on the trailing edge of the SCLK pulse
Table 6-5. JTAG Interface Pin Descriptions
See section 9 for functional description and section 10.5 for timing specifications.
Pin Name(1)
JTRST JTCLK JTDI JTDO JTMS
Type(2)
IPU I IPU O3 IPU
Pin Description
JTAG Test Reset (active low). Asynchronously resets the test access port (TAP) controller. If not used, JTRST can be held low or high. JTAG Clock, Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, JTCLK can be held low or high. JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If not used, JTDI can be held low or high. JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling edge of JTCLK. If not used, leave floating. JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave floating.
Table 6-6. Power Supply Pin Descriptions
Pin Name(1)
VDD VDDIO VSS AVDD_DL AVSS_DL VDD_OC6 VSS_OC6 AVDD_PLL1 AVSS_PLL1 AVDD_PLL2 AVSS_PLL2 AVDD_PLL3 AVSS_PLL3 AVDD_PLL4 AVSS_PLL4
Type(2)
P P P P P P P P P P P P P P P
Pin Description
Core Power Supply. 1.8V 10%. I/O Power Supply. 3.3V 5%. Ground Reference . Power Supply for OC6 Digital Logic. 1.8V 10%. Return for OC6 Digital Logic. Power Supply for Differential Output OC6POS/NEG. 1.8V 10%. Return for LVDS Differential Output OC6POS/NEG. Power Supply for Master Clock Generator APLL. 1.8V 10%. Return for Master Clock Generator APLL. Power Supply for T0 APLL. 1.8V 10%. Return for T0 APLL. Power Supply for T4 APLL. 1.8V 10%. Return for T4 APLL. Power Supply for T0 APLL2. 1.8V 10%. Return for T0 APLL2.
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Note 1: Note 2: All pin names with an overbar (e.g. RST) are active low. All pins, except power and analog pins, are CMOS/TTL unless otherwise specified in the pin description. PIN TYPES I = input pin IDIFF = input pin that is LVDS/LVPECL differential signal compatible IPD = input pin with internal 50k pull-down IPU = input pin with internal 50k pull-up I/O = input/output pin IOPD = input/output pin with internal 50k pull-down IOPU = input/output pin with internal 50k pull-up O = output pin O3 = output pin that can tri-stated (i.e. placed in a high-impedance state) ODIFF = output pin that is LVDS/LVPECL differential signal compatible P = power-supply pin All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality.
DS3105
Note 3:
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7 FUNCTIONAL DESCRIPTION
7.1 Overview
The DS3105 has five input clocks and two output clocks. There are two separate DPLLs in the device: the highperformance T0 DPLL and the simpler T4 DPLL. The T0 DPLL can generate output clocks, the T4 DPLL can be used to monitor inputs for frequency and phase. See Figure 3-1. Three of the input clock pins are single-ended and can accept clock signals from 2 kHz to 125 MHz. The other two are differential inputs that can accept clock signals up to 156.25 MHz. The differential inputs can be configured to accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals. Each input clock can be monitored continually for activity, and each can be marked unavailable or given a priority number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special modes, the highest priority valid input is automatically selected as the reference for the T0 DPLL. SRFAIL is set or cleared based on activity and/or frequency of the selected input. Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies, including, but not limited to 8 kHz, DS1, E1, 10 MHz, 19.44 MHz, and 38.88 MHz as well as Ethernet frequencies including 25 MHz, 62.5 MHz, 125 MHz and 156.25 MHz. The DPLLs can also lock to multiples of the standard direct-lock frequencies including 8 kHz. The T0 DPLL is the high-performance path with all the features needed for synchronizing a line card to dual redundant system timing cards. The T4 DPLL can be used to monitor input clock signals but it can not drive any output clocks. The T4 APLL is always connected to the T0 DPLL to provide low-jitter output frequencies from the T0 DPLL. There is also a dedicated low-jitter APLL output that operates at 312.5 MHz for 10G Ethernet applications. Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on either of the OC3 or OC6 output clock pins. Both DPLLs have these features: * Automatic reference selection based on input activity and priority * Manual reference selection/forcing * Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor * Ability to lock to several common telecom and ethernet frequencies plus multiples of any standard direct lock frequency. * Six bandwidth selections from 18 Hz to 400 Hz The T0 DPLL has these additional features not available in the T4 DPLL: * A full state machine for automatic transitions among free-run, locked, and holdover states * Optional manual reference switching mode * Non-revertive reference switching mode * Phase build-out for reference switching ("hitless") * Output vs. input phase offset control * Noise rejection circuitry for low-frequency references * Output phase alignment to input frame sync signal * Instant digital one-second averaging and free-run holdover modes * Frequency conversion between input and output using digital frequency synthesis The T4 DPLL has these additional features not available in the T0 DPLL: * Optional mode to measure the phase difference between two input clocks Typically the internal state machine controls the T0 DPLL, but manual control by system software is also available. The T4 DPLL has a simpler state machine that software can not directly control. In either DPLL, however, software can override the DPLL logic using manual reference selection. The outputs of the T0 DPLL can be connected to seven output DFS engines. See Figure 7-1. Three of these output DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and filter DPLL output jitter.
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The outputs of the APLLs are divided down to make a wide variety of possible frequencies available at the output clock pins. The output frequencies from the T0 DPLL can be synchronized to an input 2, 4 or 8 kHz sync signal (SYNC1, SYNC2 or SYNC3 input pins). The OC3 and OC6 output clocks can be configured for a variety of different frequencies that are frequency and phase locked to the T0 DPLL. The OC6 output is LVDS/LVPECL. The OC3 output is CMOS. Altogether more than 60 output frequencies are possible, ranging from 2 kHz to 312.5 MHz. The FSYNC output clock is always 8 kHz, and the MFSYNC output clock is always 2 kHz.
7.2
Device Identification and Protection
The 16-bit read-only ID field in the ID1 and ID2 registers is set to 0C21h = 3105 decimal. The device revision can be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The register set can be protected from inadvertent writes using the PROT register.
7.3
Local Oscillator and Master Clock Configuration
The T0 DPLL, the T4 DPLL and the output DFS engines operate from a 204.8 MHz master clock. The master clock is synthesized from a 12.800 MHz clock originating from a local oscillator attached to the REFCLK pin. The stability of the T0 DPLL in freerun or holdover is equivalent to the stability of the local oscillator. Selection of an appropriate local oscillator is therefore of crucial importance if the telecom standards listed in Table 1-1 are to be met. Simple XOs can be used in less stringent cases, but TCXOs or even OCXOs may be required in the most demanding applications. Careful evaluation of the local oscillator component is necessary to ensure proper performance. Contact Dallas/Maxim at telecom.support@dalsemi.com for recommended oscillators. The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8 MHz master clock from the local oscillator clock. The MCLKFREQ field in registers MCLK1 and MCLK2 specifies the frequency adjustment to be applied. The adjust can be from -771 ppm to +514 ppm in 0.0196229 ppm (i.e. ~0.02 ppm) steps.
7.4
Input Clock Configuration
The DS3105 has five input clocks, IC3 to IC6 and IC9. Table 7-1 provides summary information about each clock, including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or minimum low time of 3 ns or 30% of the clock period, whichever is smaller.
7.4.1
Signal Format Configuration
Inputs with CMOS/TTL signal format accept both TTL and 3.3V CMOS levels. One key configuration bit that affects the available frequencies is the SONSDH bit in MCR3. When SONSDH=1 (SONET mode), the 1.544 MHz frequency is available. When SONSDH=0 (SDH mode), the 2.048 MHz frequency is available. During reset the default value of this bit is latched from the SONSDH pin. Input clocks IC5 and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using the proper set of external components. The recommended LVDS termination is shown in Figure 10-1 while the recommended LVPECL termination is shown in Figure 10-2. The electrical specifications for these inputs are listed in Table 10-4. To configure these differential inputs to accept single-ended CMOS/TTL signals, use a voltage divider to bias the ICxNEG pin to approximately 1.4V and connect the single-ended signal to the ICxPOS pin. If a differential input is not used it should be left floating (one input is internally pulled high and the other internally pulled low). (See also MCR5:IC5SF and IC6SF.)
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Table 7-1. Input Clock Capabilities
Input Clock IC3 IC4 IC5 IC6 IC9
Note 1:
Signal Formats CMOS / TTL CMOS / TTL LVDS / LVPECL or CMOS/TTL LVDS / LVPECL or CMOS/TTL CMOS / TTL
Frequencies up to 125 MHz
(1)
Default Frequency 8 kHz 8 kHz
(2)
up to 125 MHz (1) up to 156.25 MHz
19.44 MHz 19.44 MHz 19.44 MHz
up to 156.25 MHz (2) up to 125 MHz (1)
Note 2:
Available frequencies for CMOS/TTL input clocks are: 2 kHz, 4 kHz, 8 kHz, 1.544 MHz (SONET mode), 2.048 MHz (SDH mode), 6.312 MHz, 6.48 MHz, 19.44 MHz, 25.0 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 62.5 MHz, 77.76 MHz, and any multiple of 2 kHz up to 125MHz. Available frequencies for LVDS/LVPECL input clocks include all CMOS/TTL frequencies in Note 1 plus any multiple of 8 kHz up to 155.52 MHz and 156.25 MHz.
7.4.2
Frequency Configuration
Input clock frequencies are configured in the FREQ field of the ICR registers. The DIVN and LOCK8K bits of these same registers specify the locking frequency mode, as shown in Table 7-2.
Table 7-2. Locking Frequency Modes
DIVN 0 0 1 1 LOCK8K 0 1 0 1 Locking Frequency Mode Direct Lock mode LOCK8K mode DIVN mode Alternate Direct Lock mode
7.4.2.1 Direct Lock Mode In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the corresponding ICR register. Direct lock mode can only be used for input clocks with these specific frequencies: 2 kHz, 4 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 5 MHz, 6.312 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 31.25 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz and 155.52 MHz. For the 155.52 MHz case, the input clock is internally divided by two, and the DPLL direct-locks at 77.76 MHz. The DIVN mode can be used to divide an input down to any of these frequencies except 155.52 MHz. MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent phase updates. 7.4.2.2 Alternate Direct Lock Mode Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used (see the FREQ field definition in the ICR register description). The alternate frequencies are included to support clock rates found in Ethernet, CMTS, wireless and GPS applications. The alternate frequencies are: 10 MHz, 25 MHz, 62.5 MHz, 125 MHz and 156.25 MHz. The frequencies 62.5 MHz, 125 MHz and 156.25 MHz are internally divided down to 31.25 MHz, while 10 MHz and 25 MHz are internally divided down to 5 MHz. 7.4.2.3 LOCK8K Mode In LOCK8K mode, an internal divider is configured to divide the selected reference down to 8 kHz. The DPLL locks to the 8 kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock frequencies: 8 kHz, 1.544 MHz, 2.048 MHz, 5 MHz, 6.312 MHz, 6.48 MHz, 19.44 MHz, 25.0 MHz, 25.92 MHz, 31.25 MHz, 38.88 MHz, 51.84 MHz, 62.5 MHz, 77.76 MHz and 155.52 MHz. LOCK8K mode is enabled for a particular input clock by setting the LOCK8K bit in the corresponding ICR register. LOCK8K mode gives a greater tolerance to input jitter when the multi-cycle phase detector is disabled because it uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
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configured using the 8KPOL bit in the TEST1 register. For 2 kHz and 4 kHz clocks the LOCK8K bit is ignored and direct-lock mode is used. 7.4.2.4 DIVN Mode In DIVN mode, an internal divider is configured from the value stored in the DIVN registers. The DIVN value must be chosen so that when the selected reference is divided by DIVN+1, the resulting clock frequency is the same as the standard direct lock frequency selected in the FREQ field of the ICR register. The DPLL locks to the output of the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 155.52 MHz. The DIVN register field can range from 0 to 65,535 inclusive. The same DIVN+1 factor is used for all input clocks configured for DIVN mode. Note that although the DIVN divider is able to divide down clock rates as high as 155.52 MHz, the CMOS/TTL inputs are only rated for a maximum clock rate of 125 MHz.
7.5
Input Clock Monitoring
Each input clock is continuously monitored for activity. Activity monitoring is described in sections 7.5.2 and 7.5.3. The valid/invalid state of each input clock is reported in the corresponding real-time status bit in registers VALSR1 or VALSR2. When the valid/invalid state of a clock changes, the corresponding latched status bit is set in registers MSR1 or MSR2, and an interrupt request occurs if the corresponding interrupt enable bit is set in registers IER1 or IER2. Input clocks marked invalid cannot be automatically selected as the reference for either DPLL.
7.5.1
Frequency Monitoring
The DS3105 monitors the frequency of each input clock and invalidates any clock whose frequency is more than 10,000 ppm away from nominal. The frequency range monitor can be disabled by clearing the MCR1.FREN bit. The frequency range measurement uses the internal 204.8 MHz master clock as the frequency reference.
7.5.2
Activity Monitoring
Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully between events and no alarm is declared. When events occur close enough together, the accumulator increments faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors. The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 through 3) in the BUCKET field of the ICR registers. Each leaky bucket configuration has programmable size, alarm declare threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers. Activity monitoring is divided into 128-ms intervals. The accumulator is incremented once for each 128ms interval in which the input clock is inactive for more than two cycles (more than four cycles for 155.52 MHz, 156.25 MHz, 125 MHz, 62.5 MHz, 25 MHz and 10 MHz input clocks). Thus the "fill" rate of the bucket is at most 1 unit per 128 ms, or approximately 8 units/second. During each period of 1, 2, 4 or 8 intervals (programmable), the accumulator decrements if no irregularities occur. Thus the "leak" rate of the bucket is approximately 8, 4, 2 or 1 units/second. A leak is prevented when a fill event occurs in the same interval. When the value of an accumulator reaches the alarm threshold (LBxU register), the corresponding ACT alarm bit is set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. When the value of an accumulator reaches the alarm clear threshold (LBxL register), the activity alarm is cleared by clearing the clock's ACT bit. The accumulator cannot increment past the size of the bucket specified in the LBxS register. The decay rate of the accumulator is specified in the LBxD register. The values stored in the leaky bucket configuration registers must have the following relationship at all times: LBxS >= LBxU > LBxL. When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the `x' in `LBxU' is the leaky bucket configuration number, 0 to 3). The minimum time to clear an activity alarm in seconds is 2^LBxD * (LBxS - LBxL) / 8. As an example, assume LBxU = 8, LBxL = 1, LBxS = 10 and LBxD = 0. The minimum time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity alarm would be 2^0 * (10 - 1) / 8 = 1.125 seconds.
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7.5.3
Selected Reference Activity Monitoring
The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL's selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference can cause unwanted jitter, wander or frequency offset on the output clocks. When anomalies occur on the selected reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from the reference until the reference is available again. By design, the regular input clock activity monitor (section 7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity monitor that detects that the frequency is within range (approximately 10,000 ppm) and detects inactivity within approximately two missing reference clock cycles (approximately four missing cycles for 156.25 MHz, 155.52 MHz, 125 MHz, 62.5 MHz, 25 MHz and 10 MHz references). When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the selected reference and sets the SRFAIL latched status bit in MSR2. The setting of the SRFAIL bit can cause an interrupt request if the corresponding enable bit is set in IER2. If MCR10:SRFPIN=1, the SRFAIL output pin follows the state of the SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference switch (see section 7.6.4). When PHLIM1:NALOL=0 (default), the T0 DPLL does not declare loss-of-lock during no-activity events. If the selected reference becomes available again before any alarms are declared by the activity monitor, then the T0 DPLL continues to track the selected reference using nearest-edge locking (180) to avoid cycle slips. When NALOL=1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL state machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt request if enabled. If the selected reference becomes available again before any alarms are declared by the activity monitor, then the T0 DPLL tracks the selected reference using phase/frequency locking (360) until phase lock is reestablished. When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If NALOL=1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an interrupt request if enabled.
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7.6
7.6.1
Input Clock Priority, Selection and Switching
Priority Configuration
During normal operation, the selected reference for the T0 DPLL is chosen automatically based on the priority rankings assigned to the input clocks in the input priority registers (IPR2 , IPR3 and IPR5). Each of these registers has priority fields for one or two input clocks. When T4T0=0 in the MCR11 register, the IPR registers specify the input clock priorities for the T0 DPLL. When T4T0=1, they have no meaning. The default input clock priorities are shown in Table 7-3. There is an inter-lock mechanism between IC3 and IC5 and between IC4 and IC6 so that only two of the inputs can be automatically selected. When IPR2.PRI3 is written with a priority other than 0, IPR3.PRI5 is automatically set to 0. When IPR3.PRI5 is written with a priority other than 0, IPR2.PRI3 is automatically set to 0. When IPR2.PRI4 is written with a priority other than 0, IPR3.PRI6 is automatically set to 0. When IPR3.PRI6 is written with a priority other than 0, IPR2.PRI4 is automatically set to 0. Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks.
Table 7-3. Default Input Clock Priorities
Input Clock IC3 IC4 IC5 IC6 IC9 T0 DPLL Default Priority 2 3 0 (off) 0 (off) 5
7.6.2
Automatic Selection Algorithm
The real-time valid/invalid state of each input clock is maintained in the VALSR1 and VALSR2 registers. The selected reference can be marked invalid for phase lock, frequency or activity. Other input clocks can be invalidated for frequency or activity. The reference selection algorithm for the T0 DPLL chooses the highest-priority valid input clock to be the selected reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table of valid inputs. The top three entries in this table and the selected reference are displayed in the PTAB1 and PTAB2 registers. When T4T0=0 in the MCR11 register, these registers indicate the highest priority input clocks for the T0 DPLL. When T4T0=1, they have no meaning. If two or more input clocks are given the same priority number then those inputs are prioritized among themselves using a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid then the next equal-priority clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is inherently non-revertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equal-priority inputs have the highest priority. An important input to the selection algorithm for the T0 DPLL is the REVERT bit in the MCR3 register. In revertive mode (REVERT=1), if an input clock with a higher priority than the selected reference becomes valid, the higherpriority reference immediately becomes the selected reference. In non-revertive mode (REVERT=0), the higherpriority reference does not immediately become the selected reference but does become the highest-priority reference in the priority table (REF1 field in the PTAB1 register). (The selection algorithm always switches to the highest-priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For many applications, non-revertive mode is preferred for the T0 DPLL because it minimizes disturbances on the output clocks due to reference switching. In non-revertive mode, planned switchover to a newly-valid higher-priority input clock can be done manually under software control. The validation of the new higher-priority clock sets the corresponding status bit in the MSR1 or MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. System software can then respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive the switchover to the higher-priority clock.
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7.6.3
Forced Selection
The T0FORCE field in the MCR2 register and the T4FORCE field in the MCR4 register provide a way to force a specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 3 to 6 and 9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally, forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT=1) the forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority input is listed as the third-highest priority (PTAB2:REF3). When the T4 DPLL is used to measure the phase difference between the T0 DPLL selected reference and another reference input by setting the T0CR1:T4MT0 bit, the T4FORCE field in the MCR4 register can be used to select the other reference input.
7.6.4
Ultra-Fast Reference Switching
By default, disqualification of the selected reference and switchover to another reference occurs when the activity monitor's inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects approximately two missing clock cycles it declares the reference failed by forcing the leaky bucket accumulator to its upper threshold (see section 7.5.2) and initiates reference switching. This is in addition to setting the SRFAIL latched status bit in MSR2 and optionally generating an interrupt request, as described in section 7.5.3. When ultrafast switching occurs, the T0 DPLL transitions to the Pre-locked 2 state, which allows switching to occur faster by bypassing the Loss-of-Lock state. The device should be in non-revertive mode when ultra-fast switching is enabled. If the device is in revertive mode, ultra-fast switching could cause excessive reference switching when the highest priority input is intermittent.
7.6.5
External Reference Switching Mode
In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by setting the EXTSW bit to 1 in the MCR10 register. In this mode, if the SRCSW pin is high, the T0 DPLL is forced to lock to input IC3 (if the priority of IC3 is non-zero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the selected input has a valid reference signal. If the SRCSW pin is low the T0 DPLL is forced to lock to input IC4 (if the priority of IC4 is non-zero in IPR2) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a valid reference signal. During reset the default value of the EXTSW bit is latched from the SRCSW pin. If external reference switching mode is enabled during reset, the default frequency tolerance (DLIMIT registers) is configured to 80 ppm rather than the normal default of 9.2 ppm. In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the selected reference whether it is valid or not. Unlike forced reference selection (section 7.6.3) this mode controls the PTAB1:SELREF field directly and is therefore not affected by the state of the MCR3:REVERT bit. During external reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2 and REF3 fields in the PTAB registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the automatic selection logic. External reference switching mode only affects the T0 DPLL.
7.6.6
Output Clock Phase Continuity During Reference Switching
If phase build out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than 30ppm then the device always complies with the GR-1244-CORE requirement that the rate of phase change must be less than 81 ns per 1.326 ms during reference switching.
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7.7
DPLL Architecture and Configuration
Both the T0 DPLL and T4 DPLL are digital PLLs. The T0 DPLL has separate analog PLLs (APLLs) as output stages as well as some outputs that are not cleaned up by an APLL. This architecture combines the benefits of both PLL types. See Figure 7-1.
Figure 7-1. DPLL Block Diagram
PLL Bypass T4 PFD and Loop Filter
0 Locking Frequency 1
T4 selected reference
T4 Foward DFS T4 Feedback DFS
ICRn:FREQ[3:0]
2K8K DFS
2
2K8K
T0CR1:T4MT0
DIG12 DFS
MCR6:DIG1SS MCR6:DIG1F[1:0]
DIG1
T4 DPLL
DIG12 DFS
MCR6:DIG2SS MCR6:DIG2F[1:0] MCR6:DIG2AF
DIG2
OC3, OC6 T4 Output APLL APLL Output Dividers
OCRm:OFREQn[3:0] OCR5:AOFn
T0 selected reference
T0 PFD and Loop Filter
T0 Foward DFS T0 Feedback DFS
ICRn:FREQ[3:0]
T4 APLL DFS
T4CR1:T4FREQ[3:0] T0CR1:T0FT4[2:0]
Locking Frequency
T0 APLL DFS
T0CR1:T0FREQ[2:0]
T0 Output APLL
APLL Output Dividers
SYNC2K
SYNC2K
T0 DPLL
T0 APLL2 DFS
T0 Output APLL2
APLL Output Dividers
FSYNC DFS
2
FSYNC, MFSYNC
OCR4:FSEN, MFSEN FSCR1:8KINV, 2KINV FSCR1:8KPOL, 2KPOL
OUTPUT DFS
FSCR2:INDEP
Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature and voltage, and (2) flexible behavior that is easily programmed via configuration registers. DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8 MHz) is multiplied up from the 12.800 MHz local oscillator clock applied to the REFCLK pin. This master clock is then digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1 nsec pk-pk. The analog PLLs filter the jitter from the DPLLs, reducing the 1 ns pk-pk jitter to less than 0.5 ns pk-pk and 60 ps RMS, typical, measured broadband (10 Hz to 1 GHz).
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The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input frequency, pull-in/hold-in range, input-to-output phase offset, phase build-out, and more. No knowledge of loop equations or gain parameters is required to configure and operate the device. No external components are required for the DPLLs or the APLLs except the high-quality local oscillator connected to the REFCLK pin. The T0 DPLL has a full free-run/locked/holdover state machine and full programmability. The secondary T4 DPLL can be used to measure frequency and phase of inputs but can not supply output clock signals.
7.7.1
T0 DPLL State Machine
The T0 DPLL has three main timing modes: locked, holdover and free-run. The control state machine for the T0 DPLL has states for each timing mode as well as three temporary states: pre-locked, pre-locked 2 and loss-of-lock. The state transition diagram is shown in Figure 7-2. Descriptions of each state are given in the paragraphs below. During normal operation the state machine controls state transitions. When necessary, however, the state can be forced using the T0STATE field of the MCR1 register. Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register. 7.7.1.1 Free-Run State Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800 MHz local oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock, which can be calibrated using the MCLKFREQ field in registers MCLK1 and MCLK2 (see section 7.3). The state machine transitions from free-run to the pre-locked state when at least one input clock is valid. 7.7.1.2 Prelocked State The pre-locked state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the selected reference. If phase lock (see section 7.7.6) is achieved for 2 seconds during this period then the state machine transitions to locked mode. If the DPLL fails to lock to the selected reference within the phase-lock time-out period specified by PHLKTO then a phase lock alarm is raised (corresponding LOCK bit set in the ISR register), invalidating the input (ICn bit goes low in VALSR registers). If another input clock is valid then the state machine re-enters the pre-locked state and tries to lock to the alternate input clock. If no other input clocks are valid for two seconds, then the state machine transitions back to the free-run state. In revertive mode (REVERT=1 in MCR3), if a higher-priority input clock becomes valid during the phase-lock timeout period then the state machine re-enters the pre-locked state and tries to lock the higher-priority input. If a phase-lock time-out period longer than 100 seconds is required for locking, then the PHLKTO register must be configured accordingly.
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Figure 7-2. T0 DPLL State Transition Diagram
Reset (selected reference invalid > 2s OR out of lock >100s) AND no valid input clock [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher-priority input)] AND valid input clock available [selected reference invalid OR (revertive mode AND valid higher-priority input)] AND valid input clock available phase-locked to selected reference > 2s
Free-Run select ref (001) all input clocks evaluated at least one input valid Pre-locked wait for <=100s (110) phase-locked to selected reference > 2s
Locked (100) phase-lock regained on selected reference within 100s loss-of-lock on selected reference
selected reference invalid > 2s AND no valid input clock available
[selected reference invalid OR (selected reference invalid > 2s (revertive mode AND valid higher-priority input) OR out of lock >100s) AND OR out of lock >100s] AND Pre-locked 2 Loss-of-Lock no valid input clock available valid input clock available wait for <=100s wait for <=100s (101) (111) (selected reference invalid > 2s OR out of lock >100s) AND no valid input clock available all input clocks evaluated at least one input valid
Holdover select ref (010)
[selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher-priority input)] AND valid input clock available
Notes: * An input clock is valid when it has no activity alarm and no phase lock alarm (see the VALSR registers and the ISR registers). * All input clocks are continuously monitored for activity. * Only the selected reference is monitored for loss of lock. * Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds. * To simply the diagram, the phase-lock time-out period is always shown as 100s, which is the default value of the PHLKTO register. Longer or shorter time-out periods can be specified as needed by writing the appropriate value to the PHLKTO register. * When selected reference is invalid and the DPLL is not in freerun or holdover, the DPLL is in a temporary holdover state.
7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the pre-locked, pre-locked 2 or loss-of-lock states when the DPLL has locked to the selected reference for at least two seconds (see section 7.7.6). In the locked state the output clocks track the phase and frequency of the selected reference. If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the Locked state. While in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding ACT bit set in the ISR register), then the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine immediately transitions to either the pre-locked 2 state (if another valid input clock is available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid). If loss-of-lock (see section 7.7.6) is declared while in the locked state then the state machine transitions to the lossof-lock state.
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7.7.1.4 Loss-of-Lock State When the loss-of-lock detectors (see section 7.7.6) indicate loss of phase lock, the state machine immediately transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds (default value of PHLKTO register) to regain phase lock. If phase lock is regained during that period for more than 2 seconds then the state machine transitions back to the locked state. If, during the phase-lock time-out period specified by PHLKTO, the selected reference is so impaired that an activity alarm is raised (corresponding ACT bit set in the ISR registers), then the selected reference is invalidated (ICn bit goes low in VALSR registers), and after being invalid for 2 seconds the state machine transitions to either the pre-locked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid). If phase lock cannot be regained by the end of the phase-lock time-out period then a phase lock alarm is raised (corresponding LOCK bit set in the ISR registers), the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine transitions to either the pre-locked 2 state (if another valid input clock is available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid). 7.7.1.5 Prelocked 2 State The pre-locked and pre-locked 2 states are similar. The pre-locked 2 state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the new selected reference. If phase lock (see section 7.7.6) is achieved for more than 2 seconds during this period then the state machine transitions to locked mode. If the DPLL fails to lock to the new selected reference within the phase-lock time-out period specified by PHLKTO then a phase lock alarm is raised (corresponding LOCK bit set in the ISR registers), invalidating the input (ICn bit goes low in VALSR registers). If another input clock is valid then the state machine re-enters the pre-locked 2 state and tries to lock to the alternate input clock. If no other input clocks are valid for 2 seconds then the state machine transitions to the holdover state. In revertive mode (REVERT=1 in MCR3), if a higher-priority input clock becomes valid during the phase-lock timeout period then the state machine re-enters the pre-locked 2 state and tries to lock to the higher-priority input. If a phase-lock time-out period longer than 100 seconds is required for locking, then the PHLKTO register must be configured accordingly. 7.7.1.6 Holdover State The device reaches the holdover state when it declares its selected reference invalid for 2 seconds and has no other valid input clocks available. During holdover the T0 DPLL is not phase locked to any input clock but instead generates its output frequency from stored frequency information acquired while it was in the locked state. When at least one input clock has been declared valid the state machine immediately transitions from holdover to the prelocked 2 state and tries to lock to the highest priority valid clock. 7.7.1.6.1 Automatic Holdover For automatic holdover (FRUNHO=0 in MCR3), the device can be further configured for instantaneous mode or averaged mode. In instantaneous mode (AVG=0 in HOCR3), the holdover frequency is set to the DPLL's current frequency 50 to 100 ms before entry into holdover (i.e. the value of the FREQ field in the FREQ1, FREQ2 and FREQ3 registers when MCR11:T4T0=0). The FREQ field is the DPLL's integral path and therefore is an average frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL's proportional path is not used in order to minimize the effect of recent phase disturbances on the holdover frequency. In averaged mode (AVG=1 in HOCR3 and FRUNHO=1 in MCR3), the holdover frequency is set to an internally averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a one-second period. The T0 DPLL indicates that it has acquired a valid holdover value by setting the HORDY status bit in VALSR2 (real-time status) and MSR4 (latched status). If the T0 DPLL must enter holdover before the 1second average is available, an instantaneous value 50 to 100 ms old from the integral path is used instead. 7.7.1.6.2 Free-Run Holdover For free-run holdover (FRUNHO=1 in MCR3), the output frequency accuracy is generated with the accuracy of the external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of the
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7.7.1.7 Mini-Holdover When the selected reference fails, the fast activity monitor (section 7.5.3) isolates the T0 DPLL from the reference within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50 to 100 ms old from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the state machine enters the holdover state. If the free-run holdover mode is set (FRUNHO=1 in MCR3), the mini-holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the MCLKFREQ field in registers MCLK1 and MCLK2 (see section 7.3).
7.7.2
T4 DPLL State Machine
The T4 DPLL state machine is simpler than the T0 state machine. The T4 DPLL does not generate any output clock signals but it can be used to measure phase between two inputs and it can lock to an input to measure the frequency and possibly stability of the input.
7.7.3
Bandwidth
The bandwidth of the T4 DPLL is configured in the T4BW register to be 18 Hz to 70 Hz. The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 18 Hz to 400 Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW=1, the T0 DPLL uses the T0ABW bandwidth during acquisition (not phase locked) and the T0LBW bandwidth when phase locked. When AUTOBW=0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition and when phase locked. When LIMINT=1 in the MCR9 register, the DPLL's integral path is limited (i.e. frozen) when the DPLL reaches minimum or maximum frequency. Setting LIMINT=1 minimizes overshoot when the DPLL is pulling in.
7.7.4
Damping Factor
The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register, while the damping factor of the T4 DPLL is configured in the DAMP field of the T4CR2 register. The reset default damping factors for both DPLLs are chosen to give a maximum jitter/wander gain peak of approximately 0.1 dB. Available settings are a function of DPLL bandwidth (configured in the T4BW, T0ABW and T0LBW registers). See Table 7-4.
Table 7-4. Damping Factors and Peak Jitter/Wander Gain
Bandwidth 18 Hz 35 Hz DAMP[2:0] Value 1 2 3, 4, 5 1 2 3 4, 5 1 2 3 4 5 Damping Factor 1.2 2.5 5 1.2 2.5 5 10 1.2 2.5 5 10 20 Gain Peak, dB 0.4 0.2 0.1 0.4 0.2 0.1 0.06 0.4 0.2 0.1 0.06 0.03
70 to 400 Hz
7.7.5
Phase Detectors
Phase detectors are used to compare a PLL's feedback clock with its input clock. Several phase detectors are available in the T0 and T4 DPLLs: * * * Phase/frequency detector (PFD) Early/late phase detector (PD2) for fine resolution Multi-cycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times 26 of 110
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These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76 MHz. The multi-cycle phase detector detects and remembers phase differences of many cycles (up to 8191 UI). When locking to 8 kHz or lower, the normal phase/frequency detectors are always used. The T0 DPLL phase detectors can be configured for normal phase/frequency locking (360 capture) or nearestedge phase locking (180 capture). With nearest-edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically switches to nearest-edge locking when the multi-cycle phase detector is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180=1 in the TEST1 register disables nearest-edge locking and forces the T0 DPLL to use phase/frequency locking. The T4 DPLL always has nearest edge locking enabled. The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2* fields of registers T0CR2 and T0CR3 for the T0 DPLL and registers T4CR2 and T4CR3 for the T4 DPLL. The reset default settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot and bandwidth. The multicycle phase detector is enabled by setting MCPDEN=1 in the PHLIM2 register. The range of the MCPD-- from 1 UI up to 8191 UI--is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase position over many clock cycles, giving high jitter tolerance. Thus the use of the MCPD is an alternative to the use of LOCK8K mode for jitter tolerance. When a DPLL is direct locking to 8 kHz, 4 kHz or 2 kHz or in LOCK8K mode, the multi-cycle phase detector is automatically disabled. When USEMCPD=1 in PHLIM2, the MCPD is used in the DPLL loop, giving faster pull-in but more overshoot. In this mode the loop has similar behavior to LOCK8K mode. In both cases large phase differences contribute to the dynamics of the loop. When enabled by MCPDEN=1, the MCPD tracks the phase position whether or not it is used in the DPLL loop. When the input clock is divided before being sent to the phase detector, the divider output clock edge gets aligned to the feedback clock edge before the DPLL starts to lock to a new input clock signal or after the input clock signal has a temporary signal loss. This helps ensure locking to the nearest input clock edge which reduces output transients and decreases lock times.
7.7.6
Loss of Phase Lock Detection
Loss of phase lock can be triggered by any of the following in both the T0 and T4 DPLLs: * The fine phase lock detector (measures phase between input and feedback clocks) * The coarse phase lock detector (measures whole cycle slips) * Hard frequency limit detector * Inactivity detector The fine phase lock detector is enabled by setting FLEN=1 in the PHLIM1 register. The fine phase limit is configured in the FINELIM field of PHLIM1. The coarse phase lock detector is enabled by setting CLEN=1 in the PHLIM2 register. The coarse phase limit is configured in the COARSELIM field of PHLIM2. This coarse phase lock detector is part of the multi-cycle phase detector (MCPD) described in section 7.7.5. The COARSELIM field sets both the MCPD range and the coarse phase limit, since the two are equivalent. If loss of phase lock should not be declared for multiple-UI input jitter then the fine phase lock detector should be disabled and the coarse phase lock detector should be used instead. The hard frequency limit detector is enabled by setting FLLOL=1 in the DLIMIT3 register. The hard limit for the T0 DPLL is configured in registers DLIMIT1 and DLIMIT2. The T4 DPLL hard limit is fixed at 80ppm. When the DPLL frequency reaches the hard limit, loss-of-lock is declared. The DLIMIT3 register also has the SOFTLIM field to specify a soft frequency limit. Exceeding the soft frequency limit does not cause loss-of-lock to be declared. When the T0 DPLL frequency reaches the soft limit the T0SOFT status bit is set in the OPSTATE register. When the T4 DPLL frequency reaches the soft limit the T4SOFT status bit is set in OPSTATE. Both the SOFT and HARD alarm limits have hysteresis as required by GR-1244.
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The inactivity detector is enabled by setting NALOL=1 in the PHLIM1 register. When this detector is enabled the DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See section 7.5.3. When the T0 DPLL declares loss of phase lock, the state machine immediately transitions to the loss-of-lock state, which sets the STATE bit in the MSR2 register and requests an interrupt if enabled. When the T4 DPLL declares loss of phase lock, the T4LOCK bit is cleared in the OPSTATE register, which sets the T4LOCK bit in the MSR3 register and requests an interrupt if enabled.
7.7.7
Phase Build-Out
7.7.7.1 Automatic Phase Build-Out in Response to Reference Switching When MCR10:PBOEN=0, phase build-out is not performed during reference switching. The T0 DPLL always locks to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference. When MCR10:PBOEN=1, phase build-out is performed during reference switching (or exiting from holdover). With PBO enabled, if the selected reference fails and another valid reference is available then the device enters a temporary holdover state in which the phase difference between the new reference and the output is measured and fed into the DPLL loop to absorb the input phase difference. Similarly, during transitions from full-holdover, mini-holdover or free-run to locked mode, the phase difference between the new reference and the output is measured and fed into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the input phase difference, the output phase transient is less than or equal to 5 ns. Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ=1. When PBO is frozen the T0 DPLL ignores subsequent phase build-out events and maintains the current phase offset between inputs and outputs. Disabling PBO while the T0 DPLL is not in the free-run or holdover states (locking or locked) will cause a phase change on the output clocks while the DPLL switches to tracking the selected reference with 0 degrees of phase error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO (which includes un-freezing) while locking or locked also causes a PBO event. 7.7.7.2 PBO Phase Offset Adjustment An uncertainty of up to 5 ns is introduced each time a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The PBOFF register specifies a small fixed offset for each phase build-out event to skew the average error toward zero and eliminate accumulation of phase shifts in one direction.
7.7.8
Input to Output (Manual) Phase Adjustment
When phase build-out is disabled (PBOEN=0 in MCR10), the OFFSET registers can be used to adjust the phase of the T0 DPLL output clocks with respect to the selected reference when locked. Output phase offset can be adjusted over a 200 ns range in 6 ps increments. This phase adjustment occurs in the feedback clock so that the output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. Simply writing to the OFFSET registers with phase build-out disabled causes a change in the input to output phase, which can be considered to be a delay adjustment. Changing the OFFSET adjustment while in free-run or holdover state will not cause an output phase offset until it exits the state and enters one of the locking states.
7.7.9
Phase Recalibration
When a phase buildout occurs, either automatic or manual, the feedback frequency synthesizer does not get an internal alignment signal to keep it aligned with the output dividers, and therefore the phase difference between input and output may become incorrect. Setting the FSCR3:RECAL bit periodically causes a recalibration process to be executed which corrects any phase error that may have occurred. During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the OFFSET registers, and then switches the DPLL out of mini-holdover. If the OFFSET registers are written during the recalibration process, the process will ramp the phase offset to the new offset value.
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7.7.10 Frequency and Phase Measurement
The T4 DPLL can measure frequency by locking onto any input. It can also measure phase between the T0 selected reference and any input by setting the T0CR1.T4MT0 bit. Accurate measurement of frequency and phase can be accomplished using the DPLLs. The T0 DPLL is always monitoring its selected reference, but the T4 DPLL can be configured as a high-resolution phase monitor. The REFCLK signal accuracy after being adjusted with MCLKFREQ is used for the frequency reference. Software can then connect the T4 DPLL to various input clocks on a rotating basis to measure phase between the T0 DPLL input and another input. See the T4FORCE field of MCR4. DPLL frequency measurements can be read from the FREQ field spanning registers FREQ1, FREQ2 and FREQ3. This field indicates the frequency of the selected reference for either the T0 DPLL or the T4 DPLL, depending on the setting of the T4T0 bit in MCR11. This frequency measurement has a resolution of 0.0003068 ppm over a 80 ppm range. The value read from the FREQ field is the DPLL's integral path value, which is an averaged measurement with an averaging time inversely proportional to DPLL bandwidth. DPLL phase measurements can be read from the PHASE field spanning registers PHASE1 and PHASE2. This field indicates the phase difference seen by the phase detector for either the T0 DPLL or the T4 DPLL, depending on the setting of the T4T0 bit in MCR11. This phase measurement has a resolution of approximately 0.703 degrees and is internally averaged with a -3 dB attenuation point of approximately 100 Hz. Thus for low DPLL bandwidths the PHASE field gives input phase wander in the frequency band from the DPLL corner frequency up to 100 Hz. This information could be used by software to compute a crude MTIE measurement. For the T0 DPLL the PHASE field always indicates the phase difference between the selected reference and the internal feedback clock. The T4 DPLL, however, can be configured to measure the phase difference between two input clocks. When T0CR1:T4MT0=1, the T4 DPLL locking capability is disabled and the T4 phase detector is configured to compare the T0 DPLL selected reference with another input by using the T4FORCE field of MCR4. This feature can be used, for example, to measure the phase difference between the T0 DPLL's selected reference and its next highest priority reference. Software could compute MTIE and TDEV with respect to the T0 DPLL selected reference for any or all of the other input clocks. When comparing the phase of the T0 selected references and a T4 forced input by setting T0CR1:T4MT0=1, several details must be kept in mind. In this mode, the T4 path receives a copy of the T0 selected reference, either directly or through a divider to 8 kHz. If the T4 selected reference is divided down to 8 kHz using LOCK8K or DIVN modes (see section 7.4.2), then the copy of the T0 selected reference is also divided down to 8 kHz. If the T4 forced input is configured for direct-lock mode, then the copy of the T0 selected reference is not divided down and must be the same frequency as the T4 forced input. See Table 7-5 for more details. (While T0CR1:T4MT0=1 the T0 path continues to lock to the T0 selected reference in the manner specified in the corresponding ICR register.)
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Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode
Locking Mode for T4 Forced Reference LOCK8K or DIVN(8K) LOCK8K or DIVN(8K) LOCK8K or DIVN(8K) LOCK8K or DIVN(8K) DIVN (not 8K) DIRECT Locking Mode for T0 Selected Reference DIRECT LOCK8K DIVN (8K) DIVN (not 8K) any any Locking Mode for Copy of T0 Selected Ref LOCK8K LOCK8K DIVN DIRECT DIRECT DIRECT Frequency of the T4 Forced Ref for T4MT0 Phase Measurement 8 kHz 8 kHz 8 kHz 8 kHz same as the T4 forced ref input frequency same as the T4 forced ref input frequency Frequency of the T0 Selected Ref for T4MT0 Phase Measurement 8 kHz 8 kHz 8 kHz 8 kHz same as the T0 selected ref input frequency(1) same as the T0 selected ref input frequency(1)
Notes: 1. In this case the T0 select reference must be the same frequency as the T4 selected reference. 2. If the T4 selected reference frequency is 8 kHz and the T0 selected reference is a different frequency, the two references can be compared by configuring the T4 forced reference for 8 kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided down to 8 kHz using either LOCK8K or DIVN mode. 3. DIVN(8K) means that the FREQ field is set to 8 kHz, DIVN(not 8K) means the FREQ field is not set to 8 kHz.
7.7.11 Input Jitter Tolerance
The device is compliant with the jitter tolerance requirements of the standards listed in Table 1-1. When using the 360 / 180 PFD, jitter can be tolerated up to the point of eye closure. Either LOCK8K mode (see section 7.4.2.2) or the multi-cycle phase detector (see section 7.7.5) should be used for high jitter tolerance.
7.7.12 Jitter Transfer
The transfer of jitter from the selected reference to the output clocks has a programmable transfer function that is determined by the DPLL bandwidth. (See section 7.7.3.) In the T0 DPLL, the 3-dB corner frequency of the jitter transfer function can be set to any of 13 positions from 0.1 Hz to 400 Hz. In the T4 DPLL the 3-dB corner frequency of the jitter transfer function can be set to various values from 18 Hz to 70 Hz.
7.7.13 Output Jitter and Wander
Several factors contribute to jitter and wander on the output clocks, including: * Jitter and wander amplitude on the selected reference (while in the locked state) * The jitter transfer characteristic of the device (while in the locked state) * The jitter and wander on the local oscillator clock signal (especially wander while in the holdover state) The DPLL in the device has programmable bandwidth (see section 7.7.3). With respect to jitter, the DPLL behaves as a low-pass filter with a programmable pole. The bandwidth of the DPLL is low enough to strongly attenuate most jitter.
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7.8
Output Clock Configuration
A total of 4 output clock pins, OC3, OC6, FSYNC and MFSYNC are available on the device. Output clocks OC3 and OC6 are individually configurable for a variety of frequencies. Output clocks FSYNC and MFSYNC are more specialized, serving as an 8 KHz frame sync (FSYNC), and a 2 KHz multi-frame sync (MFSYNC). Table 7-6 provides more detail on the capabilities of the output clock pins.
Table 7-6. Output Clock Capabilities
Output Clock OC3 OC6 OC10 OC11 Signal Format CMOS/TTL LVDS/PECL CMOS/TTL Frequencies Supported Frequency selection per section 7.8.2.3 and Table 7-7 through Table 7-13 8 KHz frame sync with programmable pulse width and polarity 2 KHz multiframe sync with programmable pulse width and polarity
7.8.1
Signal Format Configuration
Output clock OC6 is an LVDS compatible, LVPECL level-compatible output. The type of output can be selected or the output can be disabled using the OC6SF configuration bits in the MCR8 register. The LVPECL level-compatible mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers have a limited common mode signal range which can be accommodated for by using an AC coupled signal. The LVDS electrical specifications are listed in Table 10-5, and the recommended LVDS termination is shown in Figure 10-1. The LVPECL level-compatible electrical specifications are listed in Table 10-6, and the recommended LVPECL receiver termination is shown in Figure 10-3. These differential outputs can be easily interfaced to LVDS, LVPECL and CML inputs on neighboring ICs using a few external passive components. See Maxim App Note HFAN-1.0 for details. Output clocks OC3, FSYNC, and MFSYNC are CMOS/TTL signal format.
7.8.2
Frequency Configuration
The frequency of output clocks OC3 and OC6 is a function of the settings used to configure the components of the T0 PLL paths. These components are shown in the detailed block diagram of Figure 7-1. The DS3105 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8 MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS output is a coding of the clock output phase which is used by a special circuit to determine where to put the edges of the output clock between the clock edges of the master clock. The edges of the output clock, however, are not ideally located in time resulting in jitter with an amplitude typically less than 1 nsec pk-pk. 7.8.2.1 T0 and T4 DPLL Details See Figure 7-1. The T0 and T4 forward DFS blocks use the 204.8 MHz master clock and DFS technology to synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single DFS feedback clock, whereas there are two DFS output clock signals in the T0 DPLL, one for the output clocks and one for the feedback clock. In the T0 DPLL the feedback clock signal output handles phase build-out or any phase offset configured in the OFFSET registers. Thus the T0 DPLL output clock signals and the feedback clock signal are frequency locked but may have a phase offset. The T0 and T4 feedback DFS blocks are always connected to the T0 forward DFS and the T4 forward DFS, respectively. The feedback DFS blocks synthesize the appropriate locking frequencies for use by the phase-frequency detectors (PFDs). See section 7.4.2. 7.8.2.2 Output DFS and APLL Details See Figure 7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS blocks and three APLL DFS blocks. The T0 APLL, the T0 APLL2 and the T4 APLL (and their output dividers) get their frequency references from three associated APLL DFS blocks. All of the output DFS blocks are connected to the T0 DPLL.. The 2K8K DFS and FSYNC DFS blocks generate both 2 kHz and 8 kHz signals which have about 1 ns pk-pk jitter. The FSYNC (8 kHz) and MFSYNC(2 kHz) signals come from the FSYNC DFS block, which is always connected to the T0 DPLL when not in independent mode (FSCR2:INDEP=1). In independent mode they will be frequency locked, but not phase aligned with the OC3 and OC6 outputs. The 2kHz and 8 kHz signals that can be output on OC3 or OC6 always come from the 2K8K DFS, which is always connected to the T0 DPLL..
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The DIG1 DFS can generate an NxDS1 or NxE1 signal with about 1 ns pk-pk jitter. The DIG2 DFS can generate an NxDS1, NxE1, 6.312 MHz, 10 MHz or Nx19.44 MHz clock with approximately 1 ns pk-pk jitter. The frequency of the DIG1 clock is configured by the DIG1SS bit in MCR6 and the DIG1F[1:0] field in MCR7. The frequency of the DIG2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the DIG2F[1:0] field in MCR7. DIG1 and DIG2 can be independently configured for any of the frequencies shown in Table 7-7 and Table 7-8, respectively. The APLL DFS blocks and their associated output APLLs and output dividers can generate many different frequencies. The APLL DFS blocks are always connected to the T0 DPLL. The T0 APLL frequencies that can be generated are listed in Table 7-10. The T0 APLL2 frequency is always 312.500 MHz. The T4 APLL frequencies that can be generated are listed in Table 7-12. The output frequencies that can be generated from the APLL circuits are listed in Table 7-9. 7.8.2.3 OC3 and OC6 Configuration The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6: 1. Use Table 7-9 to select a set of output frequencies for each APLL, T0 and T4. Each APLL can only generate one set of output frequencies. (In SONET/SDH equipment the T0 APLL is typically configured for a frequency of 311.04 MHz in order to get Nx19.44 MHz output clocks for use on line cards.) 2. Determine from Table 7-9 the T0 and T4 APLL frequencies required for the frequency sets chosen in step 2. 3. Configure the T0FREQ field in register T0CR1 as shown in Table 7-10 for the T0 APLL frequency determined in step 3. Configure fields T4CR1:T4FREQ, T0CR1:T4APT0 and T0CR1:T0FT4 as shown in Table 7-12 for the T4 APLL frequency determined in step 3. Using Table 7-9 and Table 7-13, configure the frequencies of output clocks OC3 and OC6 in the OFREQn fields of registers OCR2 and OCR4 and the AOFn bits in the OCR5 register. Table 7-14 lists all possible frequencies for the output clocks and specifies how to configure the T0 APLL and/or the T4 APLL to obtain each frequency. Table 7-14 also indicates the expected jitter amplitude for each frequency.
Table 7-7. Digital1 Frequencies
DIG1F[1:0] Setting in MCR7 00 01 10 11 00 01 10 11 DIG1SS Setting in MCR6 0 0 0 0 1 1 1 1 Frequency, MHz 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 Jitter, pk-pk nsec, typical <1 <1 <1 <1 <1 <1 <1 <1
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Table 7-8. Digital2 Frequencies
DIG2AF Setting in MCR6 1 1 1 1 0 0 0 0 0 0 0 0 DIG2F[1:0] Setting in MCR7 00 10 00 01 00 01 10 11 00 01 10 11 DIG2SS Setting in MCR6 0 0 1 1 0 0 0 0 1 1 1 1 Frequency, MHz 6.312 10.000 19.440 38.880 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 Jitter, pk-pk nsec, typical <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL)
APLL Frequency 312.5 311.04 274.944 250 178.944 160 148.224 131.072 122.88 104 100.992 98.816 98.304 APLL / 2 156.25 155.52 137.472 125 89.472 80 74.112 65.536 61.44 52 50.496 49.408 49.152 APLL / 4 -77.76 68.376 62.5 44.736 40 37.056 32.768 30.72 26 25.248 24.704 24.576 APLL / 5 62.5 62.208 -50 -32 --24.576 20.8 ---APLL / 6 -51.84 45.824 -29.824 -24.704 -20.48 -16.832 -16.384 APLL / 8 -38.88 34.368 31.25 22.368 20 18.528 16.384 15.36 13 12.624 12.352 12.288 APLL / 10 31.25 31.104 -25 -16 --12.288 10.4 ---APLL / 12 -25.92 22.912 -14.912 -12.352 -10.24 -8.416 -8.192 APLL / 16 -19.44 17.184 -11.184 10 9.264 8.192 7.68 6.5 6.312 6.176 6.144 APLL / 20 -15.552 -12.5 -8 --6.144 5.2 ---APLL / 48 -6.48 5.728 -3.728 -3.088 -2.56 -2.104 -2.048 APLL / 64 -4.86 4.296 -2.796 2.5 2.316 2.048 1.92 -1.578 1.544 1.536
All frequencies in MHz. Common telecom, datacom and synchronization frequencies are in bold type.
Table 7-10. T0 APLL Frequency Configuration
T0 APLL Frequency, MHz
311.04 311.04 98.304 131.072 148.224 98.816 100.992 250.000
T0 APLL DFS Frequency, MHz
77.76 77.76 24.576 32.768 37.056 24.704 25.248 62.5
T0 APLL Frequency Mode
77.76 MHz 77.76 MHz 12 x E1 16 x E1 24 x DS1 16 x DS1 4 x 6312 kHz GbE / 16
T0FREQ[2:0] Setting in T0CR1
000 001 010 011 100 101 110 111
Output Jitter, pk-pk, ns, typ
< 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5
Table 7-11. T0 APLL2 Frequency Configuration
T0 APLL2 Frequency, MHz
312.500
T0 APLL2 DFS Frequency, MHz
62.500
Output Jitter, pk-pk, ns, typ
<0.5
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Table 7-12. T4 APLL Frequency Configuration
T4 APLL Frequency, MHz
Disabled 311.04 98.304 131.072 148.224 98.816 274.944 178.944 100.992 250.000 122.88 160.000 104.000 98.304 250.000 131.072 148.224 98.816 100.992
T4 APLL DFS Freq, MHz
77.76 77.76 24.576 32.768 37.056 24.704 68.736 44.736 25.248 62.500 30.720 40.000 26.000 24.576 62.500 32.768 37.056 24.704 25.248
T4 APLL Frequency Mode
Squelched 77.76 MHz 12 x E1 16 x E1 24 x DS1 16 x DS1 2 x E3 DS3 4 x 6312 kHz GbE / 16 3 x 10.24 4 x 10 2 x 13 T0 12 x E1 T0 GbE / 16 T0 16 x E1 T0 24 x DS1 T0 16 x DS1 T0 4 x 6312 kHz
T4APT0 Setting in T0CR1
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
T4FREQ[3:0] Setting in T4CR1
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 XXXX XXXX XXXX XXXX XXXX XXXX
T0FT4[2:0] Setting in T0CR1
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX 000 001 010 100 110 111
Output Jitter, pk-pk, ns, typ
< 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5
Table 7-13. OC3 and OC6 Output Frequency Selection
AOF Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OFREQ(1) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 OC3 Frequency disabled 2 kHz 8 kHz Digital2 Digital1 T0 / 48 T0 / 16 T0 / 12 T0 / 8 T0 / 6 T0 / 4 T4 / 64 T4 / 48 T4 / 16 T4 / 8 T4 / 4 disabled T0 / 64 T4 / 20 T4 / 12 T4 / 10 T4 / 5 T4 / 2 T4SELREF OC6 Frequency disabled 2 kHz 8 kHz T0 / 2 Digital1 T0 / 1 T0 / 16 T0 / 12 T0 / 8 T0 / 6 T0 / 4 T4 / 64 T4 / 48 T4 / 16 T4 / 8 T4 / 4 disabled T4 / 5 T4 / 2 T4 / 1 T02 / 5 T02 / 2 T02 / 1 T4SELREF
Note 1: The value of the OFREQn field (in the OCR2 through OCR4 registers) corresponding to output clock OCn.
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Table 7-14. Standard Frequencies for Programmable Outputs
T0 APLL Frequency, MHz T0FREQ 2 kHz 8 kHz 1.536 1.544 1.544 1.578 2.048 2.048 2.048 2.104 2.316 2.500 2.560 2.796 3.088 3.088 3.728 4.096 4.296 4.860 5.200 5.728 6.144 6.144 6.176 6.176 6.312 6.312 6.480 8.000 8.192 8.192 8.192 8.416 9.264 10.000 10.000 10.240 10.400 11.184 12.288 12.288 12.352 12.352 12.352 12.500 12.624 13.000 15.360 15.552 16.000 16.384 16.384 16.384 16.832 17.184 18.528 19.440 T4FT0 T4FREQ 2 kHz 8 kHz APLL/64 DIG1,DIG2 APLL/64 APLL/64 DIG1,DIG2 APLL/48 APLL/64 APLL/48 APLL/64 APLL/64 APLL/48 APLL/64 DIG1,DIG2 APLL/48 APLL/48 DIG1,DIG2 APLL/64 APLL/64 APLL/20 APLL/48 APLL/20 APLL/16 DIG1,DIG2 APLL/16 DIG2 APLL/16 APLL/48 APLL/20 DIG1,DIG2 APLL/12 APLL/16 APLL/12 APLL/16 DIG2 APLL/16 APLL/12 APLL/10 APLL/16 APLL/8 APLL/10 APLL/12 APLL/8 DIG1,DIG2 APLL/20 APLL/8 APLL/8 APLL/8 APLL/20 APLL/10 DIG1,DIG2 APLL/6 APLL/8 APLL/6 APLL/16 APLL/8 DIG2 T4 APLL OFREQn Jitter (typ) rms pk-pk (ps) (ns) 100 1.00 100 1.00 50 0.50 100 1.00 50 0.50 50 0.50 100 1.00 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 100 1.00 50 0.50 50 0.50 100 1.00 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 100 1.00 50 0.50 100 1.00 50 0.50 60 0.6 50 0.50 100 1.00 50 0.50 50 0.50 50 0.50 50 0.50 100 1.00 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 100 1.00 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 100 1.00 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 100 1.00
not OC6 from T0 APLL not OC6 from DIG2 not OC6 from T0 APLL not OC6 from T0 APLL not OC6 from DIG2 not OC6 from T0 APLL not OC6 from T0 APLL not OC6 from T0 APLL not OC6 from T0 APLL
12 x E1 16 x DS1 4 x 6.312 12 x E1 16 x E1 4 x 6.312 24 x DS1
12 x E1 16 x DS1 4 x 6.312 12 x E1 16 x E1 4 x 6.312 24 x DS1
12 x E1 16 x DS1 4 x 6.312 12 x E1 16 x E1 4 x 6.312 24 x DS1 4 x 10 3 x 10.24 DS3 24 x DS1 DS3 2 x E3 77.76 2 x 13 2 x E3 3 x 10.24 12 x E1 16 x DS1 4 x 6.312 77.76 4 x 10 16 x E1 24 x DS1 4 x 10 3 x 10.24 3 x 10.24 DS3 12 x E1 2 x 13 16 x DS1 GbE / 16 4 x 6.312 2 x 13 3 x 10.24 77.76 4 x 10
not OC6 from DIG2 not OC6 from T0 APLL not OC6 from DIG2 not OC6 from T0 APLL OC3 only OC3 only
24 x DS1
24 x DS1
77.76
12 x E1 not OC6 from DIG2 16 x DS1 OC3 only not OC6 from T0 APLL OC3 only not OC6 from DIG2 4 x 6.312 77.76
12 x E1 16 x DS1 4 x 6.312
12 x E1 16 x E1 4 x 6.312 24 x DS1 not OC6 OC3 only OC3 only 12 x E1 OC3 only 24 x DS1 16 x DS1 not OC6 from DIG2 OC3 only 4 x 6.312
16 x E1 24 x DS1
12 x E1 16 x DS1 GbE / 16 4 x 6.312
OC3 only OC3 only not OC6 from DIG2 12 x E1 16 x E1 4 x 6.312 24 x DS1 OC3 only 16 x E1 24 x DS1
16 x E1 2 x E3 24 x DS1
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T0 APLL Frequency, MHz 19.440 20.000 20.800 22.368 24.576 24.576 24.704 24.704 25.000 25.248 25.920 26.000 30.720 31.104 31.250 32.000 32.768 34.368 37.056 38.880 40.000 44.736 49.152 49.408 50.000 50.496 51.840 52.000 61.440 62.208 62.500 62.500 65.536 68.736 74.112 77.76 80.000 89.472 98.304 98.816 100.992 104.000 122.880 125.000 131.072 137.472 148.224 155.520 156.250 160.000 178.944 250.000 274.944 311.040 312.500 T0FREQ 77.76 T4FT0 T4FREQ 77.76 4 x 10 2 x 13 DS3 12 x E1 3 x 10.24 16 x DS1 GbE / 16 4 x 6.312 2 x 13 3 x 10.24 77.76 GbE / 16 4 x 10 16 x E1 2 x E3 24 x DS1 77.76 4 x 10 DS3 12 x E1 16 x DS1 GbE / 16 4 x 6.312 2 x 13 3 x 10.24 77.76 GbE / 16 16 x E1 2 x E3 24 x DS1 77.76 4 x 10 DS3 12 x E1 16 x DS1 4 x 6312 kHz 2 x 13 3 x 10.24 GbE / 16 16 x E1 2 x E3 24 x DS1 77.76 4 x 10 DS3 GbE / 16 77.76 T4 APLL OFREQn APLL/16 APLL/8 APLL/5 APLL/8 APLL/4 APLL/5 APLL/6 APLL/4 APLL/10 APLL/4 APLL/12 APLL/4 APLL/4 APLL/10 APLL/8 APLL/5 APLL/4 APLL/8 APLL/4 APLL/8 APLL/4 APLL/4 APLL/2 APLL/2 APLL/5 APLL/2 APLL/6 APLL/2 APLL/2 APLL/5 APLL/4 APLL/5 APLL/2 APLL/4 APLL/2 APLL/4 APLL/2 APLL/2 APLL/1 APLL/1 APLL/1 APLL/1 APLL/1 APLL/2 APLL/1 APLL/2 APLL/1 APLL/2 APLL/2 APLL/1 APLL/1 APLL/1 APLL/1 APLL/2
DS3105
Jitter (typ) rms pk-pk (ps) (ns) 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 60 0.6 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 0.50 50 50 0.50 0.50
12 x E1 24 x DS1 16 x DS1 OC3 only 4 x 6.312 77.76 OC3 only GbE / 16 16 x E1 24 x DS1 77.76 not OC3 from T0 APLL not OC3 from T0 APLL not OC3 from T0 APLL 12 x E1 16 x DS1 4 x 6.312 77.76
12 x E1 16 x DS1 GbE / 16 4 x 6.312
GbE / 16 16 x E1 24 x DS1
12 x E1 16 x DS1 GbE / 16 4 x 6.312
GbE / 16 OC6 only from T0 APLL2 not OC3 from T0 APLL not OC3 from T0 APLL 16 x E1 24 x DS1 77.76
GbE / 16 16 x E1 24 x DS1
OC6 only OC6 only OC6 only OC6 only OC6 only not OC3 from T0 APLL OC6 only OC6 only OC6 only not OC3 from T0 APLL OC6 only from T0 APLL2 OC6 only OC6 only OC6 only OC6 only OC6 only OC6 only from T0 APLL2
12 x E1 16 x DS1 4 x 6312 kHz GbE / 16 16 x E1 24 x DS1 77.76
12 x E1 16 x DS1 4 x 6312 kHz GbE / 16 16 x E1 24 x DS1
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7.8.2.4 OC3 and OC6 Default Frequency Select Pins There are two sets of frequency select pins O3F[2:0] and O6F[2:0] that control the reset default frequencies of the OC3 and OC6 output clock pins, respectively. The SONSDH pin also selects the output frequencies for some of the pin settings. There is also an interaction between O3F[2:0] and O6F[2:0] when O6F[2:0] uses some internal resource that is needed to generate certain frequencies. After reset the O3F[2:0] and O6F[2:0] pins can be used as GPIO pins and status output pins. The default output frequencies are affected by changing the register bit values of four registers: OCR2, OCR3, T0CR1, and T4CR1. The register defaults can be changed after reset using the microprocessor interface.
Table 7-15 T0CR1.T0FREQ Default Settings
O6F[2:0] =001 !=001 X O3F[2:0] =001 X !=001 SONSDH 0 1 X X T0CR1.T0FREQ 010 12 x E1 DFB 100 24 x DS1 DFB 001 77.76 AFB 001 77.76 AFB
Table 7-16 T4CR1.T4FREQ Default Settings
O6F[2:0] =001 X !=001 O3F[2:0] X =010 !=010 SONSDH 0 1 0 1 0 1 T4CR1.T4FREQ 0110 E3 0111 DS3 0110 E3 0111 DS3 0011 16 x E1 0101 16 x DS1
Table 7-17 OC6 Default Frequency Configuration
OCR3. OFREQ6 000 X 0 0000 0 34.368 1111 001 1 44.736 1110 010 X 19.44 0110 011 X 25.92 0111 100* X 38.88 1000 101 X 51.84 1001 110 X 77.76 1010 111 X 155.52 0011 * Occurs when O6F[2:0] are left floating. O6F[2:0] SONSDH Freq MHz APLL SRC --T4 T4 T0 T0 T0 T0 T0 T0
Table 7-18 OC3 Default Frequency Configuration
O3F[2:0] 000 SONSDH Freq, MHz X 0 0 2.048 001 FALSE 1 1.544 001 0 2.048 TRUE 001 1 3.088 010 0 34.736 X 010 1 44.736 X 011* X 19.44 X 100 X 25.92 X 101 X 38.88 X 110 X 51.84 X 111 X 77.76 X * Occurs when O3F[2:0] are left floating. O6F[2:0] =001 X OCR2. OFREQ3 0000 1101 1101 0111 0111 1111 1110 0110 0111 1000 1001 1010 APLL SRC --T4 T4 T0 T0 T4 T4 T0 T0 T0 T0 T0
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7.8.2.5 FSYNC and MFSYNC Configuration The FSYNC output is enabled by setting FSEN=1 in the OCR4 register, while the MFSYNC output is enabled by setting MFSEN=1 in OCR4. When disabled, these pins are driven low. When 8KPUL=0 in FSCR1, FSYNC is configured as an 8 kHz clock with 50% duty cycle. When 8KPUL=1, FSYNC is an 8 kHz frame sync that pulses low once every 125 s with pulse width equal to one cycle of output clock OC3. When 8KINV=1 in FSCR1, the clock or pulse polarity of FSYNC is inverted. When 2KPUL=0 in FSCR1, MFSYNC is configured as an 2 kHz clock with 50% duty cycle. When 2KPUL=1, MFSYNC is a 2 kHz frame sync that pulses low once every 500 s with pulse width equal to one cycle of output clock OC3. When 2KINV=1 in FSCR1, the clock or pulse polarity of MFSYNC is inverted. If either 8KPUL=1 or 2KPUL=1, then output clock OC3 must be generated from the T0 DPLL and must be configured for a frequency of 1.544 MHz or higher or the FSYNC/MFSYNC pulses may not be generated correctly. Figure 7-3 shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits have an identical effect on MFSYNC.
Figure 7-3. FSYNC 8 kHz Options
OC3 output clock FSYNC, 8KPUL=0, 8KINV=0 FSYNC, 8KPUL=0, 8KINV=1 FSYNC, 8KPUL=1, 8KINV=0 FSYNC, 8KPUL=1, 8KINV=1
7.8.2.6 Custom Output Frequencies In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be configured to generate a custom frequency. Possible custom frequencies include any multiple of 2 kHz up to 77.76 MHz and any multiple of 8 kHz up to 311.04 MHz. (An APLL must be used to achieve frequencies above 77.76 MHz.) Any of the programmable output clocks can be configured to output the custom frequency or submultiples thereof. Contact the factory at telecom.support@dalsemi.com for help with custom frequencies.
7.9
Frame and Multiframe Alignment
In addition to receiving and locking to clocks such as 19.44 MHz from system timing cards, the DS3105 can also receive and align its outputs to 2 kHz multiframe sync or 8 kHz frame sync signals from system timing cards. In this mode of operation, both a higher-speed clock (such as 6.48 MHz or 19.44 MHz) and a frame (or multiframe) sync signal from each timing card are passed to the line cards. The higher-speed clock from each timing card is connected to a regular input clock pin on the DS3105, such as IC3 or IC4, while the frame sync signal is connected to a SYNCn input pin on the DS3105, such as SYNC1 or SYNC2. The DS3105 locks to the higher-speed clock from one of the timing cards and samples the frame sync signal on the associated SYNCn pin. The DS3105 then uses the SYNCn signal to falling-edge align some or all of the output clocks. Only the falling edge of the SYNCn signal has significance. A 4 kHz or 8 kHz clock can also be used on the SYNCn pins without any changes to the register configuration, but only output clocks of 8 kHz and above are aligned in this case. Phase build-out should be disabled (PBOEN=0 in MCR10) when using SYNCn signals. When FSCR3.SOURCE!=11XX, the frame sync signal can only come from the SYNC1 pin. When FSCR3.SOURCE=11XX, the frame sync signal comes from one of SYNC1, SYNC2 or SYNC3. See section 7.9.7.
7.9.1
Sampling
By default the SYNCn signal is first sampled on the rising edge of the selected reference. This gives the most margin, given that the SYNCn signal is falling-edge aligned with the selected reference since both come from the
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same timing card. The expected timing of the SYNCn signal with respect to the sampling clock can be adjusted from 0.5 cycles early to 1 cycle late using the FSCR2:PHASEn[1:0] field.
7.9.2
Resampling
The SYNCn signal is then resampled by an internal clock derived from the T0 DPLL. The resampling resolution is a function of the frequency of the selected reference and FSCR2:OCN. When OCN=0, the resampling resolution is 6.48 MHz, which gives the highest sampling margin and also aligns clocks at 6.48 MHz and multiples thereof. When OCN=1, if the selected reference is 19.44 MHz then the resampling resolution is 19.44 MHz. If the selected reference is 38.88 MHz then the resampling resolution is 38.88 MHz. The selected reference must be either 19.44 MHz or 38.88 MHz.
7.9.3
Enable
The SYNCn signal is only allowed to align output clocks if the T0 DPLL is locked and the SYNCn signal is enabled and qualified. When FSCR3:SOURCE[3:0] != 11XX, external frame sync on the SYNC1 pin can be enabled automatically or manually. When MCR3:AEFSEN=1, external frame sync is enabled automatically when EFSEN=1 and the T0 DPLL is locked to the input clock specified by FSCR3:SOURCE[3:0]. When AEFSEN=0, external frame sync is enabled manually when MCR3:EFSEN=1 and disabled when EFSEN=0. In manual mode when EFSEN=1, FSCR3:SOURCE[3:0] is ignored and external frame sync is always enabled regardless of which input clock is the selected reference. When FSCR3:SOURCE[3:0] = 11XX, external frame sync from the SYNCn pins can be enabled when EFSEN=1 and the associated input clock becomes the selected reference. MCR3:AEFSEN can be used to automatically disable EFSEN when the selected reference changes. See section 7.9.2.
7.9.4
Qualification
The SYNCn signal is qualified when it has consistent phase and correct frequency. Specifically, it is qualified when its significant edge has been found at exact 2 kHz boundaries (when resampled as described above) for 64 cycles in a row. It is disqualified when one significant edge is not found at the 2 kHz boundary. If there is no SYNCn signal or a bad SYNCn signal, and external frame sync is enabled, the SYNCn signal will never get qualified and the 2 kHz output will simply free-run at its current 2 kHz alignment.
7.9.5
Output Clock Alignment
When the T0 DPLL is locked, external frame sync is enabled and the SYNCn signal is qualified, the SYNCn signal can be used to falling-edge align the T0 DPLL derived output clocks. Output clocks FSYNC and MFSYNC share a 2-kHz alignment generator, while the rest of the T0 DPLL derived output clocks share a second 2-kHz alignment generator. When external frame sync is not enabled or the SYNCn signal is not qualified, these 2-Hz alignment generators free-run with their existing 2-kHz alignments. When external frame sync is enabled and the SYNCn signal is qualified, the FSYNC/MFSYNC 2-kHz alignment generator is always synchronized by SYNCn, and therefore FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP=0, the T0 DPLL 2-kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2-kHz alignment generator to falling-edge align all T0-derived output clocks with SYNCn. When INDEP=1, the T0 DPLL 2-kHz alignment generator is not synchronized with the FSYNC/MFSYNC 2-kHz alignment generator and continues to free-run with its existing 2-kHz alignment. This avoids any disturbance on the T0 DPLL derived output clocks when SYNCn has a change of phase position.
7.9.6
Frame Sync Monitor
The frame sync monitor signal OPSTATE:FSMON operates in two modes, depending on the setting of the enable bit (MCR3:EFSEN). When EFSEN = 1 (external frame sync enabled) the OPSTATE:FSMON bit is set when SYNCn is not qualified and cleared when SYNCn is qualified. If SYNCn is disqualified then both 2 kHz alignment generators are immediately disconnected from SYNCn to avoid phase movement on the T0-derived outputs clocks. When OPSTATE:FSMON is set, the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the IER3 register. If SYNCn immediately stabilizes at a new phase and proper frequency, then it is requalified after 64 2 kHz cycles (nominally 32 ms). Unless system software intervenes, after SYNCn is requalified the 2 kHz alignment generators will synchronize with SYNCn's new phase alignment, causing a sudden phase movement on the output clocks. System software can avoid this sudden phase movement on the output clocks by responding to the FSMON
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interrupt within the 32 ms window with appropriate action, which might include disabling external frame sync (MCR3:EFSEN=0) to prevent the resynchronization of the 2-kHz alignment generators with SYNCn, forcing the T0 DPLL into holdover (MCR1:T0STATE=010) to avoid affecting the output clocks with any other phase hits, and possibly even disabling the master timing card and promoting the slave timing card to master since the 2 kHz signal from the master should not have such phase movements. When EFSEN = 0 (external frame sync disabled) OPSTATE:FSMON is set when the negative edge of the resampled SYNCn signal is outside of the window determined by FSCR3:MONLIM relative to the MFSYNC negative edge (or positive edge if MFSYNC is inverted) and clear when within the window. When OPSTATE:FSMON is set, the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the IER3 register.
7.9.7
SYNCn Pins
The external frame sync signal can be automatically selected from one to three separate SYNC1,2,3 pins depending on the setting of FSCR1:SYNCSRC[2:0] and which input clock is the T0 DPLL selected reference. If no associated input pin is selected as the T0 DPLL input reference, the internal SYNCn signal is inactive and will not be qualified. This function is enabled by setting FSCR3.SOURCE=11XX.
Table 7-19. External Frame Sync Source
SYNCSRC[2:0] 0XX 1X0 1X1 XXX Selected reference IC3 or IC5 IC4 or IC6 IC3 (LVTTL) IC4 (LVTTL) IC5 (LVDS) IC6 (LVDS) IC9 External Frame Sync Source SYNC1 SYNC2 SYNC1 SYNC2 SYNC1 SYNC2 SYNC3
There are three PHASEn[1:0] (n=1,2,3) select fields in the FSCR2 register. PHASE1[1:0] is associated with SYNC1, PHASE2[1:0] is associated with SYNC2, and PHASE3[1:0] is associated with SYNC3. All three SYNCn inputs can have their timing adjusted to account for frame sync signal vs. clock signal delay differences in each path. When this function is enabled with FSCR3.SOURCE=11XX, MCR3.AEFSEN, and MCR3.EFSEN, the monitoring and qualification function described in Section 7.9.4 is only performed on the selected SYNCn input pin.
7.9.8
Other Configuration Options
FSYNC and MFSYNC are always produced from the T0 DPLL. The other output clocks can also be configured as 2 kHz or 8 kHz outputs, derived from the T0 DPLL.
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7.10 Microprocessor Interface
The device presents an SPI interface on the CS, SCLK, SDI and SDO pins. SPI is a widely-used master/slave bus protocol that allows a master device and one or more slave devices to communicate over a serial bus. The DS3105 is always a slave device. Masters are typically microprocessors, ASICs or FPGAs. Data transfers are always initiated by the master device, which also generates the SCLK signal. The DS3105 receives serial data on the SDI pin and transmits serial data on the SDO pin. SDO is high-impedance except when the DS3105 is transmitting data to the bus master. Bit Order. When both bit 3 and bit 4 are low at device address 3FFFh, the register address and all data bytes are transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the register address and all data bytes are transmitted LSB first on both SDI and SDO. The reset default setting and Motorola SPI convention is MSB first. Clock Polarity and Phase. SCLK is normally low and pulses high during bus transactions. The CPHA pin sets the phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on the leading edge of the SCLK pulse and updated on SDO on the trailing edge. When CPHA = 1, data is latched in on SDI on the trailing edge of the SCLK pulse and updated on SDO on the following leading edge. SCLK does not have to toggle between accesses, i.e., when CS is high. See Figure 7-4. Device Selection. Each SPI device has its own chip-select line. To select the DS3105, pull its CS pin low. Control Word. After CS is pulled low, the bus master transmits the control word during the first sixteen SCLK cycles. In MSB-first mode the control word has the form: R/W A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BURST
where A[13:0] is the register address, R/W is the data direction bit (1=read, 0=write), and BURST is the burst bit (1=burst access, 0=single-byte access). In LSB-first mode the order of the fourteen address bits is reversed. In the discussion that follows, a control word with R/W = 1 is a read control word, while a control word with R/W = 0 is a write control word. Single-Byte Writes. See Figure 7-5. After CS goes low, the bus master transmits a write control word with BURST=0 followed by the data byte to be written. The bus master then terminates the transaction by pulling CS high. Single-Byte Reads. See Figure 7-5. After CS goes low, the bus master transmits a read control word with BURST=0. The DS3105 then responds with the requested data byte. The bus master then terminates the transaction by pulling CS high. Burst Writes. See Figure 7-5. After CS goes low, the bus master transmits a write control word with BURST=1 followed by the first data byte to be written. The DS3105 receives the first data byte on SDI, writes it to the specified register, increments its internal address register, and prepares to receive the next data byte. If the master continues to transmit, the DS3105 continues to write the data received and increment its address counter. After the address counter reaches 3FFFh it rolls over to address 0000h and continues to increment. Burst Reads. See Figure 7-5. After CS goes low, the bus master transmits a read control word with BURST=1. The DS3105 then responds with the requested data byte on SDO, increments its address counter, and prefetches the next data byte. If the bus master continues to demand data, the DS3105 continues to provide the data on SDO, increment its address counter, and pre-fetch the following byte. After the address counter reaches 3FFFh it rolls over to address 0000h and continues to increment. Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by pulling CS high. In response to early terminations, the DS3105 resets its SPI interface logic and waits for the start of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data byte, the data byte is not written. Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the DS3105 is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support this option, the bus master must not drive the SDI/SDO line when the DS3105 is transmitting.
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DS3105
Figure 7-4. SPI Clock Phase Options
CS
SCK CPHA = 0 SCK CPHA = 1 SDI/SDO MSB 6 5 4 3 2 1 LSB
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
Figure 7-5. SPI Bus Transactions
Single-Byte Write
CS SDI SDO R/W Register Address Burst
0 (Write)
Data Byte
0 (single-byte)
Single-Byte Read
CS SDI SDO R/W Register Address Burst
1 (Read) 0 (single-byte)
Data Byte
Burst Write
CS SDI SDO R/W Register Address Burst Data Byte 1
0 (Write) 1 (burst)
Data Byte N
Burst Read
CS SDI R/W Register Address Burst
1 (Read) 1 (burst)
Data Byte 1
Data Byte N
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7.11 Reset Logic
The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin JTRST. The RST pin asynchronously resets the entire device, except for the JTAG logic. When the RST pin is low all internal registers are reset to their default values, including those fields which latch their default values from, or based on, the states of configuration input pins when the RST goes high. The RST pin must be asserted once after powerup while the external oscillator is stabilizing. The MCR1:RST bit resets the entire device (except for the microprocessor interface, the JTAG logic, and the RST bit itself), but when RST is active, the register fields with pin-programmed defaults do not latch their values from, or based on, the corresponding input pins. Instead these fields are reset to the default values that were latched when the RST pin was last active. Dallas/Maxim recommends holding RST low while the external oscillator starts up and stabilizes. An incorrect reset condition could result if RST is released before the oscillator has started up completely. Important: System software must wait at least 100s after reset (RST pin or RST bit) is deasserted before initializing the device as described in section 7.13.
7.12
Power-Supply Considerations
Due to the dual-power-supply nature of the DS3105, some I/Os have parasitic diodes between a 1.8V supply and a 3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes because it could cause latchup. Two methods are available to prevent this. The first method is to place a Schottky diode external to the device between the 1.8V supply and the 3.3V supply to force the 3.3V supply to be less than one parasitic diode drop below the 1.8V supply. The second method is to ramp up the 3.3V supply first and then ramp up the 1.8V supply.
7.13 Initialization
After power-up or reset, a series of writes must be done to the DS3105 to tune it for optimal performance. This series of writes is called the initialization script. Each die revision of the DS3105 has a different initialization script. The latest initialization scripts can be obtained by downloading from the DS3105 web page, www.maximic.com/DS3105, or by emailing telecom.support@dalsemi.com. Important: System software must wait at least 100s after reset is deasserted before initializing the device
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8
REGISTER DESCRIPTIONS
The DS3105 has an overall address range from 000h to 1FFh. Table 8-1 in section 8.4 shows the register map. In each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked "--" are reserved and must be written with 0. Writing other values to these registers may put the device in a factory test mode resulting in undefined operation. Bits labeled "0" or "1" must be written with that value for proper operation. Register fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are readwrite. Register fields are described in detail in the register descriptions that follow Table 8-1.
8.1
Status Bits
The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status bits can cause an interrupt request on the INTREQ pin if enabled to do so by corresponding interrupt enable bits. ISR#.LOCK# are special-case latched status bits because they cannot create an interrupt request on the INTREQ pin and a "write 0" is needed to clear them.
8.2
Configuration Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the register definition. Configuration register bits marked "--" are reserved and must be written with 0.
8.3
Multi-Register Fields
Multi-register fields--such as FREQ[18:0] in registers FREQ1, FREQ2 and FREQ3--must be handled carefully to ensure that the bytes of the field remain consistent. A write access to a multi-register field is accomplished by writing all the registers of the field in any order, with no other accesses to the device in between. If the write sequence is interrupted by another access, none of the bytes are written and the MSR4:MRAA latched status bit is set to indicate the write was aborted. A read access from a multi-register field is accomplished by reading the registers of the field in any order, with no other accesses to the device in between. When one register of a multiregister field is read, the other register(s) in the field are frozen until after they are all read. If the read sequence is interrupted by another access, the registers of the multi-byte field are unfrozen and the MSR4:MRAA bit is set to indicate the read was aborted. For best results, interrupt servicing should be disabled in the microprocessor before a multi-register access and then enabled again after the access is complete. The multi-register fields are: Field FREQ[18:0] MCLKFREQ[15:0] HARDLIM[9:0] DIVN[15:0] OFFSET[15:0] PHASE[15:0] Registers FREQ1, FREQ2, FREQ3 MCLK1, MCLK2 DLIMIT1, DLIMIT2 DIVN1, DIVN2 OFFSET1, OFFSET2 PHASE1, PHASE2 Addresses 07, 0C, 0D 3C, 3D 41, 42 46, 47 70, 71 77, 78 Type read-only read/write read/write read/write read/write read-only
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8.4
Register Definitions
Table 8-1. Register Map
Register names are hyperlinks to register definitions. Underlined fields are read-only.
Addr Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00h ID1 ID[7:0] 01 ID2 ID[15:8] 02 REV REV[7:0] 03 TEST1 PALARM D180 -RA 0 8KPOL 0 0 05 MSR1 --IC6 IC5 IC4 IC3 --06 MSR2 STATE SRFAIL -----IC9 07 FREQ3 -----FREQ[18:16] 08 MSR3 FSMON T4LOCK ------09 OPSTATE FSMON T4LOCK T0SOFT T4SOFT -T0STATE[2:0] 0A PTAB1 REF1[3:0] SELREF[3:0] 0B PTAB2 REF3[3:0] REF2[3:0] 0C FREQ1 FREQ[7:0] 0D FREQ2 FREQ[15:8] 0E VALSR1 --IC6 IC5 IC4 IC3 --0F VALSR2 -------IC9 11 ISR2 --ACT4 LOCK4 --ACT3 LOCK3 12 ISR3 --ACT6 LOCK6 --ACT5 LOCK5 14 ISR5 ------ACT9 LOCK9 17 MSR4 -HORDY MRAA -----19 IPR2 PRI4[3:0] PRI3[3:0] 1A IPR3 PRI6[3:0] PRI5[3:0] 1C IPR5 -PRI9[3:0] 22 ICR3 DIVN LOCK8K BUCKET[1:0] FREQ[3:0] 23 ICR4 DIVN LOCK8K BUCKET[1:0] FREQ[3:0] 24 ICR5 DIVN LOCK8K BUCKET[1:0] FREQ[3:0] 25 ICR6 DIVN LOCK8K BUCKET[1:0] FREQ[3:0] 28 ICR9 DIVN LOCK8K BUCKET[1:0] FREQ[3:0] 30 VALCR1 --IC6 IC5 IC4 IC3 --31 VALCR2 -------IC9 32 MCR1 RST -FREN LOCKPIN -T0STATE[2:0] 33 MCR2 ----T0FORCE[3:0] 34 MCR3 AEFSEN LKATO XOEDGE FRUNHO EFSEN SONSDH -REVERT 35 MCR4 ----T4FORCE[3:0] 36 MCR5 RSV4 RSV3 RSV2 RSV1 --IC6SF -38 MCR6 DIG2AF DIG2SS DIG1SS -----39 MCR7 DIG2F[1:0] DIG1F[1:0] ----3A MCR8 -----OC6SF 3B MCR9 AUTOBW ---LIMINT ---3C MCLK1 MCLKFREQ[7:0] 3D MCLK2 MCLKFREQ[15:8] 40 HOCR3 AVG ----41 DLIMIT1 HARDLIM[7:0] 42 DLIMIT2 ------HARDLIM[9:8] --43 IER1 --IC6 IC5 IC4 IC3 44 IER2 STATE SRFAIL -----IC9 45 IER3 FSMON T4LOCK ------Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.
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Addr 46 47 48 4B 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 61 62 63 64 65 66 67 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 76 77 78 79 7A 7B
Register DIVN1 DIVN2 MCR10 MCR11 DLIMIT3 IER4 OCR5 LB0U LB0L LB0S LB0D LB1U LB1L LB1S LB1D LB2U LB2L LB2S LB2D LB3U LB3L LB3S LB3D OCR2 OCR3 OCR4 T4CR1 T0CR1 T4BW T0LBW T0ABW T4CR2 T0CR2 T4CR3 T0CR3 GPCR GPSR OFFSET1 OFFSET2 PBOFF PHLIM1 PHLIM2 PHMON PHASE1 PHASE2 PHLKTO FSCR1 FSCR2
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIVN[7:0] DIVN[15:0] -SRFPIN UFSW EXTSW PBOFRZ PBOEN -----T4T0 ----FLLOL SOFTLIM[6:0] ----HORDY -----AOF3 --AOF6 --LB0U[7:0] LB0L[7:0] LB0S[7:0] ------LB0D[1:0] LB1U[7:0] LB1L[7:0] LB1S[7:0] ------LB1D[1:0] LB2U[7:0] LB2L[7:0] LB2S[7:0] ------LB2D[1:0] LB3U[7:0] LB3L[7:0] LB3S[7:0] ------LB3D[1:0] ----OFREQ3[3:0] ----OFREQ6[3:0] FSEN MFSEN ----------T4FREQ[3:0] T4MT0 T4APT0 T0FT4[2:0] T0FREQ[2:0] ------T4BW[1:0] ---RSV1 RSV2 T0LBW[2:0] ---RSV1 RSV2 T0ABW[2:0] -PD2G8K[2:0] -DAMP[2:0] -PD2G8K[2:0] -DAMP[2:0] PD2EN ----PD2G[2:0] PD2EN ----PD2G[2:0] GPIO4D GPIO3D GPIO2D GPIO1D GPIO4O GPIO3O GPIO2O GPIO1O ----GPIO4 GPIO3 GPIO2 GPIO1 OFFSET[7:0] OFFSET[15:8] --PBOFF[5:0] FLEN NALOL 1 --FINELIM[2:0] CLEN MCPDEN USEMCPD -COARSELIM[3:0] NW ----PHASE[7:0] PHASE[15:8] PHLKTOM[1:0] PHLKTO[5:0] -SYNCSRC 8KINV 8KPUL 2KINV 2KPUL INDEP OCN PHASE3[1:0] PHASE2[1:0] PHASE1[1:0]
Bit 7
Bit 6
Bit 5
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Addr 7C 7D 7E
Register FSCR3 INTCR PROT
Bit 7 RECAL --
Bit 6 --
Bit 5 MONLIM[2:0] --
Bit 4
Bit 3
-LOS PROT[7:0]
Bit 2 Bit 1 SOURCE[3:0] GPO OD
Bit 0 POL
Register Map Color Coding Device Identification and Protection Local Oscillator and Master Clock Configuration Input Clock Configuration Input Clock Monitoring Input Clock Selection DPLL Configuration DPLL State Output Clock Configuration Frame/Multiframe Sync Configuration
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 ID1 Device Identification Register, LSB 00h Bit 6 0 Bit 5 1 Bit 4 ID[7:0] 0 0 0 0 Bit 3 Bit 2 Bit 1
DS3105
Bit 0 1
Bits 7 to 0: Device ID (ID[7:0]). ID[15:0] = 0C21h = 3105 decimal.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
ID2 Device Identification Register, MSB 01h Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 ID[15:8] 1 Bit 2 1 Bit 1 0 Bit 0 0
Bits 7 to 0: Device ID (ID[15:8]). See the ID1 register description.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
REV Device Revision Register 02h Bit 6 0 Bit 5 0 Bit 4 Bit 3 REV[7:0] 0 0 Bit 2 0 Bit 1 0 Bit 0 0
Bits 7 to 0: Device Revision (REV[7:0]). Contact the factory to interpret this value and determine the latest revision.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 PALARM 0 TEST1 Test Register 1 (Not Normally Used) 03h Bit 6 D180 0 Bit 5 -- 0 Bit 4 RA 1 Bit 3 0 0 Bit 2 8KPOL 1 Bit 1 0 0
DS3105
Name Default
Bit 0 0 0
Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the T0 DPLL phase lock detector. See section 7.7.6. (NOTE: This is not the same as T0STATE=Locked.) 0 = T0 DPLL phase-lock parameters are met (FLEN, CLEN, NALOL, FLLOL) 1 = T0 DPLL loss of phase lock Bit 6: Disable 180 (D180). When locking to a new reference, the T0 DPLL first tries nearest-edge locking (180) for the first two seconds. If unsuccessful it then tries full phase/frequency locking (360). Disabling the nearestedge locking can reduce lock time by up to two seconds but may cause an unnecessary phase shift (up to 360) when the new reference is close in frequency/phase to the old reference. See section 7.7.5. 0 = normal operation: try nearest-edge locking then phase/frequency locking 1 = phase/frequency locking only Bit 4: Resync Analog Dividers (RA). When this bit is set the analog output dividers are always synchronized to ensure that low-frequency outputs are in sync with the higher-frequency clock from the DPLL. 0 = synchronized for the first two seconds after power-up 1 = always synchronized Bit 3: Leave set to zero (test control). Bit 2: 8kHz Edge Polarity (8KPOL). Specifies the input clock edge to lock to on the selected reference when it is configured for LOCK8K mode. See section 7.4.2. 0 = Falling edge 1 = Rising edge Bit 1: Leave set to zero (test control). Bit 0: Leave set to zero (test control).
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -1 MSR1 Master Status Register 1 05h Bit 6 -0 Bit 5 IC6 1 Bit 4 IC5 1 Bit 3 IC4 1 Bit 2 IC3 1 Bit 1 -1
DS3105
Name Default
Bit 0 -1
Bits 5 to 2: Input Clock Status Change (IC6 to IC3). Each of these latched status bits is set to 1 when the corresponding VALSR1 status bit changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until the VALSR1 bit changes state again. When one of these latched status bits is set it can cause an interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the IER1 register. See section 7.5 for input clock validation/invalidation criteria.
Register Name: Register Description: Register Address: Bit 7 STATE 0
MSR2 Master Status Register 2 06h Bit 6 SRFAIL 0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 IC9 1
Name Default
Bit 7: T0 DPLL State Change (STATE). This latched status bit is set to 1 when the operating state of the T0 DPLL changes. STATE is cleared when written with a 1 and not set again until the operating state changes again. When STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the IER2 register. The current operating state can be read from the T0STATE field of the OPSTATE register. See section 7.7.1. Bit 6: Selected Reference Failed (SRFAIL). This latched status bit is set to 1 when the selected reference to the T0 DPLL fails, (i.e. no clock edges in two UI). SRFAIL is cleared when written with a 1. When SRFAIL is set it can cause an interrupt request on the INTREQ pin if the SRFAIL interrupt enable bit is set in the IER2 register. SRFAIL is not set in Free-run mode or Holdover mode. See section 7.5.3. Bit 0: Input Clock Status Change (IC9). This latched status bit is set to 1 when the corresponding VALSR status bit changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until the VALSR2 bit changes state again. When this latched status bit is set it can cause an interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the IER2 register. See section 7.5 for input clock validation/invalidation criteria.
Register Name: Register Description: Register Address: Bit 7 -0
FREQ3 Frequency Register 3 07h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 0 Bit 1 FREQ[18:16] 0 Bit 0 0
Name Default
Bits 2 to 0: Current DPLL Frequency (FREQ[18:16]). See the FREQ1 register description.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 FSMON 0 MSR3 Master Status Register 3 08h Bit 6 T4LOCK 1 Bit 5 -0 Bit 4 -1 Bit 3 -0 Bit 2 -0 Bit 1 -0
DS3105
Name Default
Bit 0 -0
Bit 7: Frame Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt request on the INTREQ pin if the FSMON interrupt enable bit is set in the IER3 register. See section 7.9. Bit 6: T4 DPLL Lock Status Change (T4LOCK). This latched status bit is set to 1 when the lock status of the T4 DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes again. When T4LOCK is set it can cause an interrupt request on the INTREQ pin if the T4LOCK interrupt enable bit is set in the IER3 register. See section 7.7.6.
Register Name: Register Description: Register Address: Bit 7 FSMON 1
OPSTATE Operating State Register 09h Bit 6 T4LOCK 0 Bit 5 T0SOFT 0 Bit 4 T4SOFT 0 Bit 3 -0 Bit 2 0 Bit 1 T0STATE[2:0] 0 Bit 0 1
Name Default
Bit 7: Frame Sync Input Monitor Alarm (FSMON). This real-time status bit indicates the current status of the frame sync input monitor. See section 7.9.6. 0 = no alarm 1 = alarm Bit 6: T4 DPLL Lock Status (T4LOCK). This real-time status bit indicates the current phase lock status of the T4 DPLL. See sections 7.5.3 and 7.7.6. 0 = not locked to selected reference 1 = locked to selected reference Bit 5: T0 DPLL Frequency Soft Alarm (T0SOFT). This real-time status bit indicates whether or not the T0 DPLL is tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See section 7.7.6. 0 = No alarm; frequency is within the soft alarm limits 1 = Soft alarm; frequency is outside the soft alarm limits Bit 4: T4 DPLL Frequency Soft Alarm (T4SOFT). This real-time status bit indicates whether or not the T4 DPLL is tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See section 7.7.6. 0 = No alarm; frequency is within the soft alarm limits 1 = Soft alarm; frequency is outside the soft alarm limits Bits 2 to 0: T0 DPLL Operating State (T0STATE[2:0]). This real-time status field indicates the current state of the T0 DPLL state machine. Values not listed below correspond to invalid (unused) states. See section 7.7.1. 001 = Free-run 010 = Holdover 100 = Locked 101 = Pre-locked 2 110 = Pre-locked 111 = Loss-of-lock
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 PTAB1 Priority Table Register 1 0Ah Bit 6 Bit 5 REF1[3:0] 0 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 SELREF[3:0] 0 0
DS3105
Bit 0 0
Bits 7 to 4: Highest Priority Valid Reference (REF1[3:0]). This real-time status field indicates the highest-priority valid input reference. When T4T0 = 0 in the MCR11 register, this field indicates the highest priority reference for the T0 DPLL. When T4T0=1, it indicates the highest priority reference for the T4 DPLL. Note that an input reference cannot be indicated in this field if it has been marked invalid in the VALCR1 or VALCR2 register. When the T0 DPLL is in non-revertive mode (REVERT = 0 in the MCR3 register) this field may not have the same value as the SELREF[3:0] field. See section 7.6.2. 0000 = No valid input reference available 0001 to 0010 = {unused value} 0011 = Input IC3 0100 = Input IC4 0101 = Input IC5 0110 = Input IC6 0111 to 1000 = {unused value} 1001 = Input IC9 1010 to 1111 = {unused values} Bits 3 to 0: Selected Reference (SELREF[3:0]). This real-time status field indicates the current selected reference. When T4T0=0 in the MCR11 register, this field indicates the selected reference for the T0 DPLL. When T4T0 = 1, it indicates the selected reference for the T4 DPLL. Note that an input clock cannot be indicated in this field if it has been marked invalid in the VALCR1 or VALCR2 register. When the T0 DPLL is in non-revertive mode (REVERT = 0 in the MCR3 register) this field may not have the same value as the REF1[3:0] field. See section 7.6.2. 0000 = No valid input reference available 0001 to 0010 = {unused value} 0011 = Input IC3 0100 = Input IC4 0101 = Input IC5 0110 = Input IC6 0111 to 1000 = {unused value} 1001 = Input IC9 1010 to 1111 = {unused value}
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 PTAB2 Priority Table Register 2 0Bh Bit 6 Bit 5 REF3[3:0] 0 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 REF2[3:0] 0 0
DS3105
Bit 0 0
Bits 7 to 4: Third Highest Priority Valid Reference (REF3[3:0]). This real-time status field indicates the third highest priority validated input reference. When T4T0 = 0 in the MCR11 register, this field indicates the third highest priority reference for the T0 DPLL. When T4T0 = 1, it indicates the third highest reference for the T4 DPLL. Note that an input reference cannot be indicated in this field if it has been marked invalid in the VALCR1 or VALCR2 register. See section 7.6.2. 0000 = No valid input reference available 0001 to 0010 = {unused value} 0011 = Input IC3 0100 = Input IC4 0101 = Input IC5 0110 = Input IC6 0111 to 1000 = {unused value} 1001 = Input IC9 1010 to 1111 = {unused value} Bits 3 to 0: Second Highest Priority Valid Reference (REF2[3:0]). This real-time status field indicates the second highest priority validated input reference. When T4T0=0 in the MCR11 register, this field indicates the second highest priority reference for the T0 DPLL. When T4T0=1, it indicates the second highest reference for the T4 DPLL. Note that an input reference cannot be indicated in this field if it has been marked invalid in the VALCR1 or VALCR2 register. See section 7.6.2. 0000 = No valid input reference available 0001 to 0010 = {unused value} 0011 = Input IC3 0100 = Input IC4 0101 = Input IC5 0110 = Input IC6 0111 to 1000 = {unused value} 1001 = Input IC9 1010 to 1111 = {unused value}
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 FREQ1 Frequency Register 1 0Ch Bit 6 0 Bit 5 0 Bit 4 Bit 3 FREQ[7:0] 0 0 Bit 2 0 Bit 1 0
DS3105
Bit 0 0
The FREQ1, FREQ2 and FREQ3 registers must be read consecutively. See section 8.3. Bits 7 to 0: Current DPLL Frequency (FREQ[7:0]). The full 19-bit FREQ[18:0] field spans this register, FREQ2 and FREQ3. FREQ is a 2's-complement signed integer that expresses the current frequency as an offset with respect to the master clock frequency (see section 7.3). When T4T0 = 0 in the MCR11 register, FREQ indicates the current frequency offset of the T0 DPLL. When T4T0 = 1, FREQ indicates the current frequency offset of the T4 path. Because the value in this register field is derived from the DPLL integral path, it can be considered an average frequency with a rate of change inversely proportional to the DPLL bandwidth. If LIMINT=1 in the MCR9 register, the value of FREQ freezes when the DPLL reaches its minimum or maximum frequency. The frequency offset in ppm is equal to FREQ[18:0] * 0.0003068. See section 7.7.1.6. Application Note: Frequency measurements are relative, i.e. they measure the frequency of the selected reference with respect to the local oscillator. As such, when a frequency difference exists, it is difficult to distinguish whether the selected reference is off frequency or the local oscillator is off frequency. In systems with timing card redundancy, the use of two timing cards, master and slave, can address this difficulty. Both master and slave have separate local oscillators, and each measures the selected reference. These two measurements provide the necessary information to distinguish which reference is off frequency, if we make the simple assumption that at most one reference has a significant frequency deviation at any given time (i.e. a single point of failure). If both master and slave indicate a significant frequency offset, then the selected reference must be off frequency. If the master indicates a frequency offset but the slave does not, then the master's local oscillator must be off frequency. Likewise, if the slave indicates a frequency offset but the master does not, then slave's local oscillator must be off frequency. FREQ2 Frequency Register 2 0Dh Bit 6 0 Bit 5 0 Bit 4 Bit 3 FREQ[15:8] 0 0 Bit 2 0 Bit 1 0 Bit 0 0
Register Name: Register Description: Register Address: Bit 7 Name Default 0
Bits 7 to 0: Current DPLL Frequency (FREQ[15:8]). See the FREQ1 register description.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 VALSR1 Input Clock Valid Status Register 1 0Eh Bit 6 -0 Bit 5 IC6 0 Bit 4 IC5 0 Bit 3 IC4 0 Bit 2 IC3 0 Bit 1 -0
DS3105
Name Default
Bit 0 -0
Bits 5 to 2: Input Clock Valid Status (IC6 to IC3). Each of these real-time status bits is set to 1 when the corresponding input clock is valid. An input is valid if it has no active alarms (HARD = 0, ACT = 0, LOCK = 0 in the corresponding ISR register). See also the MSR1 register and section 7.5. 0 = Invalid 1 = Valid VALSR2 Input Clock Valid Status Register 2 0Fh Bit 6 HORDY 0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 IC9 0
Register Name: Register Description: Register Address: Bit 7 -0
Name Default
Bit 6: Holdover Frequency Ready (HORDY). This real-time status bit is set to 1 when the T0 DPLL has a holdover value that has been averaged over the 1-second holdover averaging period. See the related latched status bit in MSR4 and section 7.7.1.6. Bit 0: Input Clock Valid Status (IC9). This bit has the same behavior as the bits in VALSR1 but for the IC9 clock.
Register Name: Register Description: Register Address: Bit 7 -0
ISR2 Input Status Register 2 11h Bit 6 -0 Bit 5 ACT4 1 Bit 4 LOCK4 0 Bit 3 -0 Bit 2 -0 Bit 1 ACT3 1 Bit 0 LOCK3 0
Name Default
Bit 5: Activity Alarm for Input Clock 4 (ACT4). This real-time status bit is set to 1 when the leaky bucket accumulator for IC4 reaches the alarm threshold specified in the LBxU register (where `x' in `LBxU' is specified in the BUCKET field of ICR4). An activity alarm clears the IC4 status bit in the VALSR1 register, invalidating the IC4 clock. See section 7.5.2. Bit 4: Phase Lock Alarm for Input Clock 4 (LOCK4). This status bit is set to 1 if IC4 is the selected reference and the T0 DPLL cannot phase lock to IC4 within the duration specified in the PHLKTO register (default = 100 seconds). A phase lock alarm clears the IC4 status bit in VALSR1, invalidating the IC4 clock. If LKATO = 1 in MCR3 then LOCK4 is automatically cleared after a time-out period of 128 seconds. LOCK4 is a read/write bit. System software can clear LOCK4 by writing 0 to it, but writing 1 is ignored. See section 7.7.1. Bit 1: Activity Alarm for Input Clock 3 (ACT3). This bit has the same behavior as the ACT4 bit but for the IC3 input clock. Bit 0: Phase Lock Alarm for Input Clock 3 (LOCK3). This bit has the same behavior as the LOCK4 bit but for the IC3 input clock.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 ISR3 Input Status Register 3 12h Bit 6 -0 Bit 5 ACT6 1 Bit 4 LOCK6 0 Bit 3 -0 Bit 2 -0 Bit 1 ACT5 1
DS3105
Name Default
Bit 0 LOCK5 0
This register has the same behavior as the and ISR2 registers, but for input clocks IC5 and IC6.
Register Name: Register Description: Register Address: Bit 7 -0
ISR5 Input Status Register 5 14h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 ACT9 1 Bit 0 LOCK9 0
Name Default
This register has the same behavior as the ISR2 register, but for input clock IC9.
Register Name: Register Description: Register Address: Bit 7 -0
MSR4 Master Status Register 4 17h Bit 6 HORDY 0 Bit 5 MRAA 0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 -0
Name Default
Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the T0 DPLL has a holdover value that has been averaged over the 1-second holdover averaging period. HORDY is cleared when written with a 1. When HORDY is set it can cause an interrupt request on the INTREQ pin if the HORDY interrupt enable bit is set in the IER4 register. See section 7.7.1.6. Bit 5: Multi-Register Access Aborted (MRAA). This latched status bit is set to 1 when a multi-byte access (read or write) is interrupted by another access to the device. MRAA is cleared when written with a 1. MRAA cannot cause an interrupt to occur. See section 8.3.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 IPR2 Input Priority Register 2 19h Bit 6 Bit 5 PRI4[3:0] 0 1 Bit 4 1 Bit 3 0 Bit 2 Bit 1 PRI3[3:0] 0 1
DS3105
Bit 0 0
Bits 7 to 4: Priority for Input Clock 4 (PRI4[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0=0, PRI4 configures IC4's priority for the T0 DPLL. See section 7.6.1. When PRI4 is written with a value > 0, IPR3:PRI6 will be forced to 0 (disabled). 0000 = IC4 unavailable for selection. 0001-1111 = IC4 relative priority Bits 3 to 0: Priority for Input Clock 3 (PRI3[3:0]). Priority 0001 is highest; priority 1111 is lowest. When MCR11:T4T0=0, PRI3 configures IC3's priority for the T0 DPLL. See section 7.6.1. When PRI3 is written with a value > 0, IPR3:PRI5 will be forced to 0 (disabled). 0000 = IC3 unavailable for selection. 0001-1111 = IC3 relative priority
Register Name: Register Description: Register Address: Bit 7 Name Default 0
IPR3 Input Priority Register 3 1Ah Bit 6 Bit 5 PRI6[3:0] 0 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 PRI5[3:0] 0 0 Bit 0 0
This register has the same behavior as IPR2 but for input clocks IC5 and IC6.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
IPR5 Input Priority Register 5 1Ch Bit 6 -0 0 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PRI9[3:0] 1 0 Bit 0 0
This register has the same behavior as IPR2 but for input clock IC9.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 DIVN 0 ICR3, ICR4, ICR5, ICR6, ICR9 Input Configuration Register 3, 4, 5, 6, 9 22h, 23h, 24h, 25h, 28h Bit 6 LOCK8K 0 Bit 5 Bit 4 BUCKET[1:0] 0 0 Bit 3 Bit 2 Bit 1 FREQ[3:0] see below
DS3105
Bit 0
Name Default
These registers are identical in function. ICRx is the control register for input clock ICx. Bit 7: DIVN Mode (DIVN). When DIVN is set to 1 and LOCK8K=0, the input clock is divided down by a programmable pre-divider. The resulting output clock is then passed to the DPLL. All input clocks for which DIVN=1 are divided by the factor specified in DIVN1 and DIVN2. When DIVN=1 and LOCK8K=0 in an ICR register, the FREQ field of that register must be set to the input frequency divided by the divide factor. When DIVN=1 and LOCK8K=1 in an ICR register, the FREQ field of that register is decoded as the alternate frequencies. See sections 7.4.2.2 and 7.4.2.4. 0 = Disabled 1 = Enabled Bit 6: LOCK8K Mode (LOCK8K). When LOCK8K is set to 1 and DIVN=0, the input clock is divided down by a preset pre-divider. The resulting output clock, which is always 8 kHz, is then passed to the DPLL. LOCK8K is ignored when DIVN=0 and FREQ[3:0] = 1001 (2 kHz) or 1010 (4 kHz). When DIVN=1 and LOCK8K=1 in an ICR register, the FREQ field of that register is decoded as the alternate frequencies. See sections 7.4.2.2 and 7.4.2.3 0 = Disabled 1 = Enabled Bits 5 to 4: Leaky Bucket Configuration (BUCKET[1:0]). Each input clock has leaky bucket accumulator logic in its activity monitor. The LBxy registers at addresses 50h to 5Fh specify four different leaky bucket configurations. Any of the four configurations can be specified for the input clock. See section 7.5.2. 00 = leaky bucket configuration 0 01 = leaky bucket configuration 1 10 = leaky bucket configuration 2 11 = leaky bucket configuration 3 Bits 3 to 0: Input Clock Frequency (FREQ[3:0]). When DIVN=0 and LOCK8K=0 (standard direct-lock mode), this field specifies the input clock's nominal frequency for direct-lock operation. When DIVN=0 and LOCK8K=1 (LOCK8K mode) this field specifies the input clock's nominal frequency for LOCK8K operation. When DIVN=1 and LOCK8K=0 (DIVN mode), this field specifies the frequency after the DIVN divider (i.e. input frequency divided by DIVN + 1). When DIVN=1 and LOCK8K=1 (alternate direct-lock frequencies), this field specifies the input clock's nominal frequency for direct-lock operation. DIVN=0 or LOCK8K=0: (Standard direct-lock mode, LOCK8K mode, or DIVN mode) 0000 = 8 kHz 0001 = 1544 or 2048 kHz (as determined by SONSDH bit in the MCR3 register) 0010 = 6.48 MHz 0011 = 19.44 MHz 0100 = 25.92 MHz 0101 = 38.88 MHz 0110 = 51.84 MHz 0111 = 77.76 MHz 1000 = 155.52 MHz (only valid for LVDS inputs) 1001 = 2 kHz 1010 = 4 kHz 1011 = 6312 kHz 1100 = 5 MHz 1101 = 31.25 MHz (not a multiple of 8 kHz and therefore not valid for LOCK8K mode) 1110 to 1111 = undefined
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Preliminary. Subject to Change Without Notice. DIVN=1 and LOCK8K=1: (Alternate direct-lock frequency decode) 0000 = 10 MHz (internally divided down to 5 MHz) 0001 = 25 MHz (internally divided down to 5 MHz) 0010 = 62.5 MHz (internally down to 31.25 MHz) 0011 = 125 MHz (internally down to 31.25 MHz) 0100 = 156.25 MHz (differential inputs only. internally divided down to 31.25 MHz) 0101 to 1111 = undefined FREQ[3:0] Default Values: ICR3 - ICR4: 0000b ICR5 - ICR9: 0011b
DS3105
Register Name: Register Description: Register Address: Bit 7 -1
VALCR1 Input Clock Valid Control Register 1 30h Bit 6 -0 Bit 5 IC6 1 Bit 4 IC5 1 Bit 3 IC4 1 Bit 2 IC3 1 Bit 1 -0 Bit 0 -0
Name Default
Bits 5 to 2: Input Clock Valid Control (IC6 to IC3). These control bits can be used to force input clocks to be considered invalid. If a clock is invalidated by one of these control bits it will not appear in the priority table in the PTAB1 and PTAB2 registers, even if the clock is otherwise valid. These bits are useful when system software needs to force clocks to be invalid in response to OAM commands. Note that setting a VALCR bit low has no effect on the corresponding bit in the VALSR registers. See sections 7.6.2. 0 = Force invalid 1 = Don't force invalid; determine validity normally VALCR2 Input Clock Valid Control Register 2 31h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 IC9 1
Register Name: Register Description: Register Address: Bit 7 -0
Name Default
Bit 0: Input Clock Valid Control (IC9). This bit has the same behavior as the bits in VALCR1 but for the IC9 input clock.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 RST 0 MCR1 Master Configuration Register 1 32h Bit 6 -0 Bit 5 FREN 1 Bit 4 LOCKPIN 0 Bit 3 -0 Bit 2 0 Bit 1 T0STATE[2:0] 0
DS3105
Bit 0 0
Name Default
Bit 7: Device Reset (RST). When this bit is high the entire device is held in reset, and all register fields, except the RST bit itself, are reset to their default states. When RST is active, the register fields with pin-programmed defaults do not latch their values from the corresponding input pins. Instead these fields are reset to the default values that were latched from the pins when the RST pin was last active. See section 7.11. 0 = Normal operation 1 = Reset Bit 5: Frequency Range Detect Enable (FREN). When this bit is high the frequency of each input clock is measured and used to quickly declare the input inactive. 0 = Frequency Range Detect disabled 1 = Frequency Range Detect enabled Bit 4: T0 DPLL LOCK Pin Enable (LOCKPIN). When this bit is high the LOCK pin indicates when the T0 DPLL state machine is in the LOCK state (OPSTATE.T0STATE=100). 0 = LOCK pin is not driven 1 = LOCK pin is driven high when the T0 DPLL is in the Lock state Bits 2 to 0: T0 DPLL State Control (T0STATE[2:0]). This field allows the T0 DPLL state machine to be forced to a specified state. The state machine will remain in the forced state, and therefore cannot react to alarms and other events, as long as T0STATE is not equal to 000. See section 7.7.1. 000 = Automatic (normal state machine operation) 001 = Free-run 010 = Holdover 011 = {unused value} 100 = Locked 101 = Pre-locked 2 110 = Pre-locked 111 = Loss-of-lock
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 MCR2 Master Configuration Register 2 33h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 1 Bit 2 Bit 1 T0FORCE[3:0] 1 1
DS3105
Bit 0 1
Name Default
Bits 3 to 0: T0 DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to force a specified input clock to be the selected reference for the T0 DPLL. Internally this is accomplished by forcing the clock to have the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT=1) the forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. In nonrevertive mode the forced clock only becomes the selected reference when the existing selected reference is invalidated or made unavailable for selection. When a reference is forced, the activity monitor for that input and the T0 DPLL's loss-of-lock timeout logic all continue to operate and affect the relevant ISR, VALSR and MSR register bits. However, when the reference is declared invalid the T0 DPLL is not allowed to switch to another input clock. The T0 DPLL continues to respond to the fast activity monitor, transitioning to mini-holdover in response to short-term events and to full holdover in response to longer events. See section 7.6.3. 0000 = Automatic source selection (normal operation) 0001 = {unused value, undefined} 0010 = {unused value, undefined} 0011 = Force to IC3 0100 = Force to IC4 0101 = Force to IC5 0110 = Force to IC6 0111 = {unused value} 1000 = {unused value, undefined} 1001 = Force to IC9 1010 to 1110 = {unused values} 1111 = Automatic source selection (normal operation)
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 AEFSEN 1 MCR3 Master Configuration Register 3 34h Bit 6 LKATO 1 Bit 5 XOEDGE 0 Bit 4 FRUNHO 0 Bit 3 EFSEN 1 Bit 2 SONSDH see below Bit 1 -1
DS3105
Name Default
Bit 0 REVERT 0
Bit 7: Auto External Frame Sync Enable (AEFSEN). This bit has two modes depending on the SOURCE field of FSCR3. See section 7.9. SOURCE != 11XX: 0 = EFSEN bit (bit 3 below) enables and disables the external frame sync on the SYNCn pin 1 = The external frame sync is enabled when EFSEN=1 and the T0 DPLL is locked to the input clock specified in the SOURCE field of FSCR3. SOURCE = 11XX: 0 = External frame sync enabled according to EFSEN bit. 1 = When the selected reference changes the EFSEN bit clears and the external frame sync is disabled. (EFSEN bit must be set to enable it again.) Bit 6: Phase Lock Alarm Timeout (LKATO). This bit controls how phase alarms on input clocks can be terminated. Phase alarms are indicated by the LOCK bits in ISR registers. 0 = Phase alarms on input clocks can only be cancelled by software. 1 = Phase alarms are automatically cancelled after a time-out period of 128 seconds. Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See section 7.3. 0 = Rising edge 1 = Falling edge Bit 4: Free-Run Holdover (FRUNHO). When this bit is set to 1 the T0 DPLL holdover frequency is set to 0 ppm so the output frequency accuracy is set by the external oscillator accuracy. This effects both mini-holdover and the holdover state. 0 = Digital holdover 1 = Free-Run holdover, 0 ppm Bit 3: External Frame Sync Enable (EFSEN). When this bit is set to 1 the T0 DPLL looks for a frame sync pulse on the SYNCn pin(s). When FSCR3.SOURCE=11XX the function of this bit can be modified according to the setting of the AEFSEN bit. See the AEFSEN bit description above for more information. See section 7.9. 0 = Disable external frame sync; ignore SYNCn pin(s) 1 = Enable external frame sync on SYNCn pin(s) Bit 2: SONET or SDH Frequencies (SONSDH). This bit specifies the clock rate for input clocks with FREQ=0001 in the ICR registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See section 7.4.2. 0 = 2048 kHz 1 = 1544 kHz. Bit 0: Revertive Mode (REVERT). This bit configures the T0 DPLL for revertive or non-revertive operation. (The T4 DPLL is always revertive). In revertive mode, if an input clock with a higher priority than the selected reference becomes valid, the higher-priority reference immediately becomes the selected reference. In non-revertive mode the higher-priority reference does not immediately become the selected reference but does become the highestpriority reference in the priority table (REF1 field in the PTAB1 register). See section 7.6.2.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -1 MCR4 Master Configuration Register 4 35h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 0 Bit 2 Bit 1 T4FORCE[3:0] 0 0
DS3105
Bit 0 0
Name Default
Bits 3 to 0: T4 DPL Force Selected Reference (T4FORCE[3:0]). This field provides a way to force a specified input clock to be the selected reference for the T4 DPLL. Internally this is accomplished by forcing the clock to have the highest priority (as specified in PTAB1:REF1). Since the T4 DPLL always operates in revertive mode, the forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. When a reference is forced, the activity monitor for that input continues to operate and affect the relevant ISR, VALSR and MSR register bits. See section 7.6.3. 0000 = Automatic source selection (normal operation) 0001 = {unused value, undefined} 0010 = {unused value, undefined} 0011 = Force to IC3 0100 = Force to IC4 0101 = Force to IC5 0110 = Force to IC6 0111 = {unused value, undefined} 1000 = {unused value, undefined} 1001 = Force to IC9 1010 to 1110 = {unused value, undefined} 1111 = Automatic source selection (normal operation) MCR5 Master Configuration Register 5 36h Bit 6 RSV3 0 Bit 5 RSV2 0 Bit 4 RSV1 0 Bit 3 -0 Bit 2 -0 Bit 1 IC6SF 0 Bit 0 -0
Register Name: Register Description: Register Address: Bit 7 RSV4 0
Name Default
Bit 7: Reserved Bit 4 (RSV4). This bit is reserved for future use, it can be written to and read back. Bit 6: Reserved Bit 3 (RSV3). This bit is reserved for future use, it can be written to and read back. Bit 5: Reserved Bit 2 (RSV2). This bit is reserved for future use, it can be written to and read back. Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back. Bit 1: Input Clock 6 Signal Format (IC6SF). For backward compatibility this bit can be written to and read back, but it does not affect the IC6POS/NEG inputs pins. See Section 7.4.1.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 DIG2AF 0 MCR6 Master Configuration Register 6 38h Bit 6 DIG2SS see below Bit 5 DIG1SS see below Bit 4 -1 Bit 3 -1 Bit 2 -1 Bit 1 -1
DS3105
Name Default
Bit 0 -1
Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies. 0 = Digital2 NxE1 or NxDS1 frequency specified by DIG2SS and MCR7:DIG2F. 1 = Digital2 6.312 MHz, 10 MHz or Nx19.44 MHz frequency specified by DIG2SS and MCR7:DIG2F. Bit 6: Digital2 SONET or SDH Frequencies (DIG2SS). This bit specifies whether the clock rates generated by the Digital2 clock synthesizer are multiples of 1.544 MHz (SONET-compatible) or multiples of 2.048 MHz (SDHcompatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the MCR7 register. When RST=0 the default value of this bit is latched from the SONSDH pin. DIG2AF=0: 0 = Multiples of 2048 kHz 1 = Multiples of 1544 kHz DIG2AF=1: 6.312 MHz, 10 MHz or Nx19.44 MHz Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whether the clock rates generated by the Digital1 clock synthesizer are multiples of 1544 kHz (SONET-compatible) or multiples of 2048 kHz (SDHcompatible). The specific multiple is set in the DIG1F field of the MCR7 register. When RST=0 the default value of this bit is latched from the SONSDH pin. 0 = Multiples of 2048 kHz 1 = Multiples of 1544 kHz
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: MCR7 Master Configuration Register 7 39h Bit 5 Bit 4 DIG1F[1:0] 0 0 Bit 3 -1 Bit 2 -0 Bit 1 -0
DS3105
Name Default
Bit 7 Bit 6 DIG2F[1:0] 0 0
Bit 0 -0
Bits 7 to 6: Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS and MCR6:DIG2AF configure the frequency of the Digital2 clock synthesizer. DIG2AF=0 DIG2SS = 0 DIG2SS = 1 00 = 1544 kHz 00 = 2048 kHz 01 = 3088 kHz 01 = 4096 kHz 10 = 6176 kHz 10 = 8192 kHz 11 = 12352 kHz 11 = 16384 kHz DIG2AF=1 DIG2SS = 1 DIG2SS = 0 00 = 19.44 MHz 00 = 6.312 MHz 01 = 38.88 MHz 01 = undefined 10 = undefined 10 = 10 MHz 11 = undefined 11 = undefined
Bits 5 to 4: Digital1 Frequency (DIG1F[1:0]). This field and MCR6:DIG1SS configure the frequency of the Digital1 clock synthesizer. DIG1SS = 1 00 = 1544 kHz 01 = 3088 kHz 10 = 6176 kHz 11 = 12352 kHz DIG1SS = 0 00 = 2048 kHz 01 = 4096 kHz 10 = 8192 kHz 11 = 16384 kHz
Register Name: Register Description: Register Address: Bit 7 -0
MCR8 Master Configuration Register 8 3Ah Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 Bit 0 OC6SF[1:0] 1 0
Name Default
Bits 1 to 0: Output Clock 6 Signal Format (OC6SF[1:0]). See section 7.8.1. 00 = Output disabled 01 = 3V LVPECL level compatible 10 = 3V LVDS compatible (default) 11 = 3V LVDS compatible
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 AUTOBW 1 MCR9 Master Configuration Register 9 3Bh Bit 6 -1 Bit 5 -1 Bit 4 -1 Bit 3 LIMINT 1 Bit 2 -0 Bit 1 -1
DS3105
Name Default
Bit 0 -1
Bit 7: Automatic Bandwidth Selection (AUTOBW). See section 7.7.3. 0 = Always selects locked bandwidth from the T0LBW register 1 = Automatically selects either locked bandwidth (T0LBW register) or acquisition bandwidth (T0ABW register) as appropriate Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL's integral path is limited (i.e. frozen) when the DPLL reaches minimum or maximum frequency, as set by the HARDLIM field in DLIMIT1 and DLIMIT2. When the integral path is frozen, the current DPLL frequency in registers FREQ1, FREQ2 and FREQ3 is also frozen. Setting LIMINT=1 minimizes overshoot when the DPLL is pulling in. See section 7.7.3. 0 = Don't freeze integral path at min/max frequency 1 = Freeze integral path at min/max frequency
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 1 MCLK1 Master Clock Frequency Adjustment Register 1 3Ch Bit 6 0 Bit 5 0 Bit 4 Bit 3 MCLKFREQ[7:0] 1 1 Bit 2 0 Bit 1 0
DS3105
Bit 0 1
The MCLK1 and MCLK2 registers must be read consecutively and written consecutively. See section 8.3. Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field spans this register and MCLK2. MCLKFREQ is an unsigned integer that adjusts the frequency of the internal 204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to +514ppm and -771 ppm. The master clock adjustment has the effect of speeding up the master clock with a positive adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to REFCLK has an offset of +1 ppm then the adjustment should be -1 ppm to correct the offset. The formulas below translate adjustments to register values and vice versa. The default register value of 39,321 corresponds to 0 ppm. See section 7.3. MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321 adjustment_in_ppm = ( MCLKFREQ[15:0] - 39,321 ) * 0.0196229 MCLK2 Master Clock Frequency Adjustment Register 2 3Dh Bit 6 0 Bit 5 0 Bit 4 Bit 3 MLCKFREQ[15:8] 1 1 Bit 2 0 Bit 1 0 Bit 0 1
Register Name: Register Description: Register Address: Bit 7 Name Default 1
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[15:8]). See the MCLK1 register description.
Register Name: Register Description: Register Address: Bit 7 AVG 1
HOCR3 Holdover Configuration Register 3 40h Bit 6 -0 Bit 5 -0 Bit 4 -0 1 0 Bit 3 Bit 2 Bit 1 -0 Bit 0 0
Name Default
See section 8.3 for important information about writing and reading this register. Bit 7: Averaging (AVG). When this bit is set to 1 the T0 DPLL uses the averaged frequency value during holdover mode. When FRUNHO=1 in the MCR3 register, this bit is ignored. See section 7.7.1.6. 0 = Not averaged frequency; holdover frequency is either freerun (FRUNHO=1) or instantaneously frozen 1 = Averaged frequency over the last 1 second while locked to the input
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 DLIMIT1 DPLL Frequency Limit Register 1 41h Bit 6 1 Bit 5 1 Bit 4 Bit 3 HARDLIM[7:0] 1 0 Bit 2 1 Bit 1 1
DS3105
Bit 0 0
The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See section 8.3. Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register and DLIMIT2. HARDLIM is an unsigned integer that specifies the hard frequency limit or pull-in/hold-in range of the T0 DPLL. When frequency limit detection is enabled by setting FLLOL=1 in the DLIMIT3 register, if the DPLL frequency exceeds the hard limit then the DPLL declares loss-of-lock. The hard frequency limit in ppm is HARDLIM[9:0] * 0.0782. The default value is normally 9.2 ppm. If external reference switching mode is enabled during reset (see section 7.6.5), the default value is configured to 79.794 ppm (3FFh). See section 7.7.6.
Register Name: Register Description: Register Address: Bit 7 -0
DLIMIT2 DPLL Frequency Limit Register 1 42h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 Bit 0 HARDLIM[9:8] 0 0
Name Default
Bits 1 to 0: DPLL Hard Frequency Limit (HARDLIM[9:8]). See the DLIMIT1 register description.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 IER1 Interrupt Enable Register 1 43h Bit 6 -0 Bit 5 IC6 0 Bit 4 IC5 0 Bit 3 IC4 0 Bit 2 IC3 0 Bit 1 -0
DS3105
Name Default
Bit 0 -0
Bits 5 to 2 Interrupt Enable for Input Clock Status Change (IC6 to IC3. Each of these bits is an interrupt enable control for the corresponding bit in the MSR1 register. 0 = Mask the interrupt 1 = Enable the interrupt IER2 Interrupt Enable Register 2 44h Bit 6 SRFAIL 0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 IC9 0
Register Name: Register Description: Register Address: Bit 7 STATE 0
Name Default
Bit 7: Interrupt Enable for T0 DPLL State Change (STATE). This bit is an interrupt enable for the STATE bit in the MSR2 register. 0 = Mask the interrupt 1 = Enable the interrupt Bit 6: Interrupt Enable for Selected Reference Failed (SRFAIL). This bit is an interrupt enable for the SRFAIL bit in the MSR2 register. 0 = Mask the interrupt 1 = Enable the interrupt Bit 0: Interrupt Enable for Input Clock Status Change (IC9). This bit is an interrupt enable control for the IC9 bit in the MSR2 register. 0 = Mask the interrupt 1 = Enable the interrupt Register Name: Register Description: Register Address: Bit 7 FSMON 0 IER3 Interrupt Enable Register 3 45h Bit 6 T4LOCK 0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 -0
Name Default
Bit 7: Interrupt Enable for Frame Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable for the FSMON bit in the MSR3 register. 0 = Mask the interrupt 1 = Enable the interrupt Bit 6: Interrupt Enable for the T4 DPLL Lock Status Change (T4LOCK). This bit is an interrupt enable for the T4LOCK bit in the MSR3 register. 0 = Mask the interrupt 1 = Enable the interrupt
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 1 DIVN1 DIVN Register 1 46h Bit 6 1 Bit 5 1 Bit 4 Bit 3 DIVN[7:0] 1 1 Bit 2 1 Bit 1 1
DS3105
Bit 0 1
The DIVN1 and DIVN2 registers must be read consecutively and written consecutively. See section 8.3. Bits 7 to 0: DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode. The frequency is divided by DIVN[15:0] + 1. See section 7.4.2.4.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
DIVN2 DIVN Register 2 47h Bit 6 0 Bit 5 1 Bit 4 Bit 3 DIVN[15:8] 1 1 Bit 2 1 Bit 1 1 Bit 0 1
Bits 7 to 0: DIVN Factor (DIVN[15:8]). See the DIVN1 register description.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -1 MCR10 Master Configuration Register 10 48h Bit 6 SRFPIN 0 Bit 5 UFSW 0 Bit 4 EXTSW see below Bit 3 PBOFRZ 0 Bit 2 PBOEN 1 Bit 1 -0
DS3105
Name Default
Bit 0 -0
Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the SRFAIL pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the system a very fast indication of the failure of the current reference. See section 7.5.3. 0 = SRFAIL pin disabled (not driven) 1 = SRFAIL pin enabled Bit 5: Ultra-Fast Switching Mode (UFSW). See section 7.6.4. 0 = Disabled 1 = Enabled. The current reference source is disqualified after less than three missing clock cycles. Bit 4: External Reference Switching Mode (EXTSW). This bit enables external reference switching mode. In this mode, if the SRCSW pin is high the T0 DPLL is forced to lock to input IC3 (if the priority of IC3 is non-zero) or IC5 (if the priority of IC3 is zero) whether or not the selected input has a valid reference signal. If the SRCSW pin is low the device is forced to lock to input IC4 (if the priority of IC4 is non-zero) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a valid reference signal. During reset the default value of this bit is latched from the SRCSW pin. This mode only controls the T0 DPLL. The T4 DPLL is not affected. See section 7.6.5. 0 = Normal operation 1 = External switching mode Bit 3: Phase Build-Out Freeze (PBOFRZ). This bit freezes the current input-output phase relationship and does not allow further phase build-out events to occur. This bit affects phase build-out in response to reference switching (section 7.7.7.1). 0 = Not frozen 1 = Frozen Bit 2: Phase Build-Out Enable (PBOEN). When this bit is set to 1 a phase build-out event occurs every time the T0 DPLL changes to a new reference, including exiting the Holdover and Free-run states. When this bit is set to 0, the T0 DPLL locks to the new source with zero degrees of phase difference. See section 7.7.7.
Register Name: Register Description: Register Address: Bit 7 -0
MCR11 Master Configuration Register 11 4Bh Bit 6 -0 Bit 5 -0 Bit 4 T4T0 0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 -0
Name Default
Bit 4: T4 or T0 Path Select (T4T0). This bit specifies which path is being accessed when reads or writes are made to the following registers: PTAB1, PTAB2, FREQ1, FREQ2, FREQ3, IPR2, IPR3, IPR5, PHASE1 and PHASE2. 0 = T0 path 1 = T4 path
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 FLLOL 1 DLIMIT3 DPLL Frequency Limit Register 3 4Dh Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 SOFTLIM[6:0] 1 Bit 2 1 Bit 1 1
DS3105
Bit 0 0
Name Default
Bit 7: Frequency Limit Loss of Lock (FLLOL). When this bit is set to 1, the T0 DPLL and the T4 DPLL internally declare loss-of-lock when their hard limits are reached. The T0 DPLL hard frequency limit is set in the HARDLIM[9:0] field in the DLIMIT1 and DLIMIT2 registers. The T4 DPLL hard frequency limit is fixed at 80ppm. See section 7.7.6. 0 = DPLL declares loss-of-lock normally 1 = DPLL also declares loss-of-lock when the hard frequency limit is reached Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM6:0]). This field is an unsigned integer that specifies the soft frequency limit for the T0 DPLL and the T4 DPLL. The soft limit is only used for monitoring; exceeding this limit does not cause loss-of-lock. The limit in ppm is SOFTLIM[6:0] * 0.628. The default value is 8.79 ppm. When the T0 DPLL frequency reaches the soft limit the T0SOFT status bit is set in the OPSTATE register. When the T4 DPLL frequency reaches the soft limit the T4SOFT status bit is set in OPSTATE. See section 7.7.6. IER4 Interrupt Enable Register 4 4Eh Bit 6 HORDY 0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 -0 Bit 0 -0
Register Name: Register Description: Register Address: Bit 7 -0
Name Default
Bit 6: Interrupt Enable for Holdover Frequency Ready (HORDY). This bit is an interrupt enable for the HORDY bit in the MSR4 register. 0 = Mask the interrupt 1 = Enable the interrupt
Register Name: Register Description: Register Address: Bit 7 -0
OCR5 Output Configuration Register 1 4Fh Bit 6 -0 Bit 5 AOF6 0 Bit 4 -0 Bit 3 -0 Bit 2 AOF3 0 Bit 1 -0 Bit 0 -0
Name Default
Bit 5: Alternate Output Frequency Mode Select 6 (AOF6). This bit controls the decoding of the OCR3.OFREQ6 field for the OC6 pin. 0 = Standard decodes 1 = Alternate decodes Bit 2: Alternate Output Frequency Mode Select 3 (AOF3). This bit controls the decoding of the OCR2.OFREQ3 field for the OC3 pin. 0 = Standard decodes 1 = Alternate decodes
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 LB0U Leaky Bucket 0 Upper Threshold Register 50h Bit 6 0 Bit 5 0 Bit 4 Bit 3 LB0U[7:0] 0 0 Bit 2 1 Bit 1 1
DS3105
Bit 0 0
Bits 7 to 0: Leaky Bucket 0 Upper Threshold (LB0U[7:0]). When the leaky bucket accumulator is equal to the value stored in this field, the activity monitor declares an activity alarm by setting the input clock's ACT bit in the appropriate ISR register. Registers LB0U, LB0L, LB0S and LB0D together specify leaky bucket configuration 0. See section 7.5.2. LB0L Leaky Bucket 0 Lower Threshold Register 51h Bit 6 0 Bit 5 0 Bit 4 Bit 3 LB0L[7:0] 0 0 Bit 2 1 Bit 1 0 Bit 0 0
Register Name: Register Description: Register Address: Bit 7 Name Default 0
Bits 7 to 0: Leaky Bucket 0 Lower Threshold (LB0L[7:0]). When the leaky bucket accumulator is equal to the value stored in this field, the activity monitoring logic clears the activity alarm (if previously declared) by clearing the input clock's ACT bit in the appropriate ISR register. Registers LB0U, LB0L, LB0S and LB0D together specify leaky bucket configuration 0. See section 7.5.2. LB0S Leaky Bucket 0 Size Register 52h Bit 6 0 Bit 5 0 Bit 4 Bit 3 LB0S[7:0] 0 1 Bit 2 0 Bit 1 0 Bit 0 0
Register Name: Register Description: Register Address: Bit 7 Name Default 0
Bits 7 to 0: Leaky Bucket 0 Size (LB0S[7:0]). This field specifies the maximum value of the leaky bucket. The accumulator cannot increment past this value. Registers LB0U, LB0L, LB0S and LB0D together specify leaky bucket configuration 0. See section 7.5.2. LB0D Leaky Bucket 0 Decay Rate Register 53h Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 Bit 0 LB0D[1:0] 0 1
Register Name: Register Description: Register Address: Bit 7 -0
Name Default
Bits 1 to 0: Leaky Bucket 0 Decay Rate (LB0D[1:0]). This field specifies the decay or "leak" rate of the leaky bucket accumulator. For each period of 1, 2, 4 or 8 128-ms intervals in which no irregularities are detected on the input clock, the accumulator decrements by 1. Registers LB0U, LB0L, LB0S and LB0D together specify leaky bucket configuration 0. See section 7.5.2. 00 = decrement every 128 ms (8 units/second) 01 = decrement every 256 ms (4 units/second) 10 = decrement every 512 ms (2 units/second) 11 = decrement every 1024 ms (1 unit/second)
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default 0 LB1U, LB2U, LB3U Leaky Bucket 1/2/3 Upper Threshold Register 54h, 58h, 5Ch Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 LBxU[7:0] 0 Bit 2 1 Bit 1 1
DS3105
Bit 0 0
Bits 7 to 0: Leaky Bucket `x' Upper Threshold (LBxU[7:0]). See the LB0U register description. Registers LB1U, LB1L, LB1S and LB1D together specify leaky bucket configuration 1. Registers LB2U, LB2L, LB2S and LB2D together specify leaky bucket configuration 2. Registers LB3U, LB3L, LB3S and LB3D together specify leaky bucket configuration 3.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
LB1L, LB2L, LB3L Leaky Bucket 1/2/3 Lower Threshold Register 55h, 59h, 5Dh Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 LBxL[7:0] 0 Bit 2 1 Bit 1 0 Bit 0 0
Bits 7 to 0: Leaky Bucket `x' Lower Threshold (LBxL[7:0]). See the LB0L register description. Registers LB1U, LB1L, LB1S and LB1D together specify leaky bucket configuration 1. Registers LB2U, LB2L, LB2S and LB2D together specify leaky bucket configuration 2. Registers LB3U, LB3L, LB3S and LB3D together specify leaky bucket configuration 3.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
LB1S, LB2S, LB3S Leaky Bucket 1/2/3 Size Register 56h, 5Ah, 5Eh Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 LBxS[7:0] 1 Bit 2 0 Bit 1 0 Bit 0 0
Bits 7 to 0: Leaky Bucket `x' Size (LBxS[7:0]). See the LB0S register description. Registers LB1U, LB1L, LB1S and LB1D together specify leaky bucket configuration 1. Registers LB2U, LB2L, LB2S and LB2D together specify leaky bucket configuration 2. Registers LB3U, LB3L, LB3S and LB3D together specify leaky bucket configuration 3.
Register Name: Register Description: Register Address: Bit 7 -0
LB1D, LB2D, LB3D Leaky Bucket 1/2/3 Decay Rate Register 57h, 5Bh, 5Fh Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 -0 Bit 2 -0 Bit 1 Bit 0 LBxD[1:0] 0 1
Name Default
Bits 1 to 0: Leaky Bucket `x' Decay Rate (LBxD[1:0]). See the LB0D register description. Registers LB1U, LB1L, LB1S and LB1D together configure leaky bucket algorithm 1. Registers LB2U, LB2L, LB2S and LB2D together configure leaky bucket algorithm 2. Registers LB3U, LB3L, LB3S and LB3D together configure leaky bucket algorithm 3.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 0 0 OCR2 Output Configuration Register 2 61h Bit 6 0 0 Bit 5 0 0 Bit 4 0 0 Bit 3 Bit 2 Bit 1 OFREQ3[3:0] see below
DS3105
Bit 0
Name Default
Bits 3 to 0: Output Frequency of OC3 (OFREQ3[3:0]). This field specifies the frequency of output clock OC3. The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The Digital1 and Digital2 frequencies are configured in the MCR7 register. See section 7.8.2.3. The default frequency is set by the O3F[2:0] bits, see Table 7-18. The decode of this field is controlled by the value of the OCR5.AOF3 bit. AOF3=0: (standard decodes) 0000 = Output disabled (i.e. low) 0001 = 2 kHz 0010 = 8 kHz 0011 = Digital2 (see Table 7-8) 0100 = Digital1 (see Table 7-7) 0101 = T0 APLL frequency divided by 48 0110 = T0 APLL frequency divided by 16 0111 = T0 APLL frequency divided by 12 1000 = T0 APLL frequency divided by 8 1001 = T0 APLL frequency divided by 6 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided by 8 1111 = T4 APLL frequency divided by 4 AOF3=1: (alternate decodes) 0000 = Output disabled (i.e. low) 0001 = T0 APLL frequency divided by 64 0010 = T4 APLL frequency divided by 20 0011 = T4 APLL frequency divided by 12 0100 = T4 APLL frequency divided by 10 0101 = T4 APLL frequency divided by 5 0110 = T4 APLL frequency divided by 2 0111 = T4 selected reference (after dividing) 1000 to 1111 = undefined
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 Name Default OCR3 Output Configuration Register 3 62h Bit 6 Bit 5 OFREQ6[3:0] see below Bit 4 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0
DS3105
Bit 0 0 0
Bits 7 to 4: Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output OC6. The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The Digital1 and Digital2 frequencies are configured in the MCR7 register. See section 7.8.2.3. The default frequency is set by the O6F[2:0] bits, see Table 7-17. The decode of this field is controlled by the value of the OCR5.AOF6 bit. AOF6=0: (standard decodes) 0000 = Output disabled (i.e. low) 0001 = 2 kHz 0010 = 8 kHz 0011 = T0 APLL frequency divided by 2 0100 = Digital1 (see Table 7-7) 0101 = T0 APLL frequency 0110 = T0 APLL frequency divided by 16 0111 = T0 APLL frequency divided by 12 1000 = T0 APLL frequency divided by 8 1001 = T0 APLL frequency divided by 6 1010 = T0 APLL frequency divided by 4 1011 = T4 APLL frequency divided by 64 1100 = T4 APLL frequency divided by 48 1101 = T4 APLL frequency divided by 16 1110 = T4 APLL frequency divided by 8 1111 = T4 APLL frequency divided by 4 AOF6=1: (alternate decodes) 0000 = Output disabled (i.e. low) 0001 = T4 APLL frequency divided by 5 0010 = T4 APLL frequency divided by 2 0011 = T4 APLL frequency 0100 = T0 APLL2 frequency divided by 5 0101 = T0 APLL2 frequency divided by 2 0110 = T0 APLL2 frequency 0111 = T4 selected reference (after dividing) 1000 to 1111 = undefined
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 MFSEN 1 OCR4 Output Configuration Register 4 63h Bit 6 FSEN 1 Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 Bit 1 0 0
DS3105
Name Default
Bit 0 0 0
Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2 kHz output on the MFSYNC pin. See section 7.8.2.5. 0 = Disabled, driven low 1 = Enabled, output is 2 kHz Bit 6: FSYNC Enable (FSEN). This configuration bit enables the 8 kHz output on the FSYNC pin. See section 7.8.2.5. 0 = Disabled, driven low 1 = Enabled, output is 8 kHz
Register Name: Register Description: Register Address: Bit 7 -0 Bit 6 -0
T4CR1 the T4 DPLL Configuration Register 1 64h Bit 5 -0 Bit 4 -0 Bit 3 Bit 2 Bit 1 T4FREQ[3:0] see below Bit 0
Name Default
Bits 3 to 0: T4 APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0=0, this field configures the T4 APLL DFS frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL which in turn affects the available output frequencies on the output clock pins (see the registers). See section 7.8.2. The default value of this field is controlled by the O6F[2:0] and O3F[2:0] pins as described in Table 7-16.
T4FREQ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1100 - 1111
T4 APLL DFS Frequency APLL output disabled 77.76 MHz 24.576 MHz (12 x E1) 32.768 MHz (16 x E1) 37.056 MHz (24 x DS1) 24.704 MHz (16 x DS1) 68.736 MHz (2 x E3) 44.736 MHz (DS3) 25.248 MHz (4 x 6312 kHz) 62.500 MHz (GbE / 16) 30.720 MHz (3 x 10.24) 40.000 MHz (4 x 10 MHz) 26.000 MHz (2 x 13 MHz) {unused values}
T4 APLL Frequency (4 x T4 APLL DFS) Disabled, output is low 311.04 MHz (4 x 77.76 MHz) 98.304 MHz (48 x E1) 131.072 MHz (64 x E1) 148.224 MHz (96 x DS1) 98.816 MHz (64 x DS1) 274.944 MHz (8 x E3) 178.944 MHz (4 x DS3) 100.992 MHz (16 x 6312 kHz) 250.000 MHz (GbE / 4) 122.880 MHz (12 x 10.24) 160.000 MHz (16 x 10 MHz) 104.000 MHz (8 x 13 MHz) {unused values}
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 T4MT0 0 T0CR1 T0 DPLL Configuration Register 1 65h Bit 6 T4APT0 0 Bit 5 0 Bit 4 T0FT4[2:0] 0 Bit 3 0 Bit 2 Bit 1 T0FREQ[2:0] see below
DS3105
Bit 0
Name Default
Bit 7: T4 Measure T0 Phase (T4MT0). When this bit is set to 1 the T4 phase detector is configured to measure the phase difference between the selected T0 DPLL input clock and the selected the T4 DPLL input clock. See section 7.7.10. 0 = T4 can lock to an input to measure frequency 1 = Enable T4-measure-T0-phase mode Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, T4CR1:T4FREQ configures the T4 APLL DFS frequency. The T4 APLL DFS frequency affects the frequency of the T4 APLL which in turn affects the available output frequencies on the output clock pins (see the registers). When this bit is set to 1, the frequency of the T4 APLL DFS is configured by the T0CR1:T0FT4[2:0] field below. See section 7.8.2. 0 = T4 APLL frequency is determined by T4FREQ 1 = T4 APLL frequency is determined by T0FT4
9
Bits 5 to 3: T0 Frequency to T4 APLL (T0FT4[2:0]). When the T4APT0 bit is set to 1, this field specifies the frequency of the T4 APLL DFS. This frequency can be different than the frequency specified by T0CR1:T0FREQ. See section 7.8.2. T0FT4 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = T4 APLL DFS Frequency 24.576 MHz (12 x E1) 62.500 MHz (GbE / 16) 32.768 MHz (16 x E1) {unused value} 37.056 MHz (24 x DS1) {unused value} 24.704 MHz (16 x DS1) 25.248 MHz (4 x 6312 kHz) T4 APLL Frequency (4 x T4 APLL DFS) 98.304 MHz (48 x E1) 250.000 MHz (GbE / 4) 131.072 MHz (64 x E1) {unused value} 148.224 MHz (96 x DS1) {unused value} 98.816 MHz (64 x DS1) 100.992 MHz (16 x 6312 kHz)
Bits 2 to 0: T0 DPLL Output Frequency (T0FREQ[2:0]). This field configures the T0 APLL DFS frequency. The T0 APLL DFS frequency affects the frequency of the T0 APLL, which in turn affects the available output frequencies on the output clock pins (see the registers). See section 7.8.2. The default frequency is controlled by the O6F[2:0] and O3F[2:0] pins as described in Table 7-15. T0FREQ 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = T0 APLL DFS Frequency 77.76 MHz 77.76 MHz 24.576 MHz (12 x E1) 32.768 MHz (16 x E1) 37.056 MHz (24 x DS1) 24.704 MHz (16 x DS1) 25.248 MHz (4 x 6312 kHz) 62.500 MHz (GbE / 16) T0 APLL Frequency (4 x T0 APLL DFS) 311.04 MHz (4 x 77.76 MHz) 311.04 MHz (4 x 77.76 MHz) 98.304 MHz (48 x E1) 131.072 MHz (64 x E1) 148.224 MHz (96 x DS1) 98.816 MHz (64 x DS1) 100.992 MHz (16 x 6312 kHz) 250.000 MHz (GbE / 4)
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 0 0 Bit 6 0 0 T4BW T4 Bandwidth Register 66h Bit 5 0 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0
DS3105
Name Default
Bit 1 Bit 0 T4BW[1:0] 0 0
Bits 2 to 0: T4 DPLL Bandwidth (T4BW[2:0]). See section 7.7.3. 000 = 18 Hz 001 = 35 Hz 010 = 70 Hz 011 = {unused value, undefined}
Register Name: Register Description: Register Address: Bit 7 0 0 Bit 6 0 0
T0LBW T0 DPLL Locked Bandwidth Register 67h Bit 5 0 0 Bit 4 RSV1 0 Bit 3 RSV2 0 Bit 2 0 Bit 1 T0LBW[2:0] 0 Bit 0 0
Name Default
Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back. Bit 3: Reserved Bit 2 (RSV2). This bit is reserved for future use, it can be written to and read back. Bits 2 to 0: T0 DPLL Locked Bandwidth (T0LBW[2:0]). This field configures the bandwidth of the T0 DPLL when locked to an input clock. When AUTOBW=0 in the MCR9 register, the T0LBW bandwidth is used for acquisition and for locked operation. When AUTOBW=1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth is used for locked operation. See section 7.7.3. 111 = 18 Hz 000 = 35 Hz (default) 001 = 70 Hz 010 = {unused value, undefined} 011 = 18 Hz 100 = 120 Hz 101 = 250 Hz 110 = 400 Hz
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 0 0 Bit 6 0 0 T0ABW T0 DPLL Acquisition Bandwidth Register 69h Bit 5 0 0 Bit 4 RSV1 0 Bit 3 RSV2 0 Bit 2 0 Bit 1 T0LBW[2:0] 0
DS3105
Bit 0 1
Name Default
Bit 4: Reserved Bit 1 (RSV1). This bit is reserved for future use, it can be written to and read back. Bit 3: Reserved Bit 2 (RSV2). This bit is reserved for future use, it can be written to and read back. Bits 2 to 0: T0 DPLL Acquisition Bandwidth (T0ABW[2:0]). This field configures the bandwidth of the T0 DPLL when acquiring lock. When AUTOBW=0 in the MCR9 register, the T0LBW bandwidth is used for is used for acquisition and for locked operation. When AUTOBW=1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth is used for locked operation. See section 7.7.3. 111 = 18 Hz 000 = 35 Hz 001 = 70 Hz (default) 010 = {unused value, undefined} 011 = 18 Hz 100 = 120 Hz 101 = 250 Hz 110 = 400 Hz
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 Bit 6 0 T4CR2 T4 Configuration Register 2 6Ah Bit 5 PD2G8K[2:0] 0 Bit 4 1 Bit 3 -0 Bit 2 0 Bit 1 DAMP[2:0] 1
DS3105
Bit 0 1
Name Default
Bits 6 to 4: Phase Detector 2 Gain 8 kHz (PD2GA8K[2:0]). This field specifies the gain of the T4 phase detector 2 with an input clock of 8 kHz or less. This value is only used if automatic gain selection is enabled by setting PD2EN=1 in the T4CR3 register. See section 7.7.5. Bits 2 to 0: Damping Factor (DAMP[2:0]). This field configures the damping factor of the T4 DPLL. Damping factor is a function of both DAMP[2:0] and the T4 DPLL bandwidth (T4BW register). The default value corresponds to a damping factor of 5. See section 7.7.4. 35 Hz 18 Hz 001 = 1.2 1.2 010 = 2.5 2.5 011 = 5 5 100 = 5 10 101 = 5 10 000, 110 and 111 = {unused values} The gain peak for each damping factor is shown below: Damping Factor 1.2 2.5 5 10 20 Gain Peak 0.4 dB 0.2 dB 0.1 dB 0.06 dB 0.03 dB 70 Hz 1.2 2.5 5 10 20
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 Bit 6 0 T0CR2 T0 Configuration Register 2 6Bh Bit 5 PD2G8K[2:0] 0 Bit 4 1 Bit 3 -0 Bit 2 0 Bit 1 DAMP[2:0] 1
DS3105
Bit 0 1
Name Default
Bits 6 to 4: Phase Detector 2 Gain, 8 kHz (PD2G8K[2:0]). This field specifies the gain of the T0 phase detector 2 with an input clock of 8 kHz or less. This value is only used if automatic gain selection is enabled by setting PD2EN=1 in the T0CR3 register. See section 7.7.5. Bits 2 to 0: Damping Factor (DAMP[2:0]). This field configures the damping factor of the T0 DPLL. Damping factor is a function of both DAMP[2:0] and the T0 DPLL bandwidth (T0ABW and T0LBW). The default value corresponds to a damping factor of 5. See section 7.7.4. 001 = 010 = 011 = 100 = 101 = 4 Hz 5 5 5 5 5 8 Hz 2.5 5 5 5 5 18 Hz 1.2 2.5 5 5 5 35 Hz 1.2 2.5 5 10 10 70 Hz 1.2 2.5 5 10 20
000, 110 and 111 = {unused values} The gain peak for each damping factor is shown below: Damping Factor 1.2 2.5 5 10 20 Gain Peak 0.4 dB 0.2 dB 0.1 dB 0.06 dB 0.03 dB
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 PD2EN 1 Bit 6 1 T4CR3 T4 Configuration Register 3 6Ch Bit 5 -0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 PD2G[2:0] 1
DS3105
Bit 0 0
Name Default
Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the T4 phase detector 2 is enabled and the gain is determined by the input locking frequency. If the frequency is greater than 8 kHz, the gain is set by the PD2G field. If the frequency is less or equal to 8 kHz, the gain is set by the PD2G8K field in the T4CR2 register See section 7.7.5. 0 = Disable 1 = Enable Bits 2 to 0: Phase Detector 2 Gain (PD2G[2:0]). This field specifies the gain of the T4 phase detector 2 when the input frequency is greater than 8 kHz. This value is only used if automatic gain selection is enabled by setting PD2EN=1. See section 7.7.5.
Register Name: Register Description: Register Address: Bit 7 PD2EN 1 Bit 6 1
T0CR3 T0 Configuration Register 3 6Dh Bit 5 -0 0 0 0 Bit 4 Bit 3 Bit 2 Bit 1 PD2G[2:0] 1 Bit 0 0
Name Default
Bit 7: Phase Detector 2 Gain Enable (PD2EN). When this bit is set to 1, the T0 phase detector 2 is enabled and the gain is determined by the input locking frequency. If the frequency is greater than 8 kHz, the gain is set by the PD2G field. If the frequency is less or equal to 8 kHz, the gain is set by the PD2G8K field in the T0CR2 register See section 7.7.5. 0 = Disable 1 = Enable Bits 2 to 0: Phase Detector 2 Gain (PD2G[2:0]). This field specifies the gain of the T0 phase detector 2 when the input frequency is greater than 8 kHz. This value is only used if automatic gain selection is enabled by setting PD2EN=1. See section 7.7.5.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 GPIO4D 0 GPCR GPIO Configuration Register 6Eh Bit 6 GPIO3D 0 Bit 5 GPIO2D 0 Bit 4 GPIO1D 0 Bit 3 GPIO4O 0 Bit 2 GPIO3O 0 Bit 1 GPIO2O 0
DS3105
Name Default
Bit 0 GPIO1O 0
Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 is an input its current state can be read from GPSR:GPIO4. When GPIO4 is an output, its value is controlled by the GPIO4O configuration bit. 0 = Input 1 = Output Bit 6: GPIO3 Direction (GPIO3D). This bit configures the data direction for the GPIO3 pin. When GPIO3 is an input its current state can be read from GPSR:GPIO3. When GPIO3 is an output, its value is controlled by the GPIO3O configuration bit. 0 = Input 1 = Output Bit 5: GPIO2 Direction (GPIO2D). This bit configures the data direction for the GPIO2 pin. When GPIO2 is an input its current state can be read from GPSR:GPIO2. When GPIO2 is an output, its value is controlled by the GPIO2O configuration bit. 0 = Input 1 = Output Bit 4: GPIO1 Direction (GPIO1D). This bit configures the data direction for the GPIO1 pin. When GPIO1 is an input its current state can be read from GPSR:GPIO1. When GPI13 is an output, its value is controlled by the GPIO1O configuration bit. 0 = Input 1 = Output Bit 3: GPIO4 Output Value (GPIO4O). When GPIO4 is configured as an output (GPIO4D=1) then this bit specifies the output value. 0 = Low 1 = High Bit 2: GPIO3 Output Value (GPIO3O). When GPIO3 is configured as an output (GPIO3D=1) then this bit specifies the output value. 0 = Low 1 = High Bit 1: GPIO2 Output Value (GPIO2O). When GPIO2 is configured as an output (GPIO2D=1) then this bit specifies the output value. 0 = Low 1 = High Bit 0: GPIO1 Output Value (GPIO1O). When GPIO1 is configured as an output (GPIO1D=1) then this bit specifies the output value. 0 = Low 1 = High
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 Bit 6 -0 GPSR GPIO Status Register 6Fh Bit 5 -0 Bit 4 -0 Bit 3 GPIO4 0 Bit 2 GPIO3 1 Bit 1 GPIO2 0
DS3105
Name Default
Bit 0 GPIO1 0
Bit 3: GPIO4 State (GPIO4). This bit indicates the current state of the GPIO4 pin. 0 = low 1 = high Bit 2: GPIO3 State (GPIO3). This bit indicates the current state of the GPIO3 pin. 0 = low 1 = high Bit 2: GPIO2 State (GPIO2). This bit indicates the current state of the GPIO2 pin. 0 = low 1 = high Bit 1: GPIO1 State (GPIO1). This bit indicates the current state of the GPIO1 pin. 0 = low 1 = high
Register Name: Register Description: Register Address: Bit 7 Name Default 0 Bit 6 0
OFFSET1 Phase Offset Register 1 70h Bit 5 0 Bit 4 Bit 3 OFFSET[7:0] 0 0 Bit 2 0 Bit 1 0 Bit 0 0
The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See section 8.3. Bits 7 to 0: Phase Offset (OFFSET[7:0]). The full 16-bit OFFSET[15:0] field spans this register and the OFFSET2 register. OFFSET is a 2's-complement signed integer that specifies the desired phase offset between the output clocks and the selected input reference. The phase offset in picoseconds is equal to OFFSET[15:0] * actual_internal_clock_period / 211. If the internal clock is at its nominal frequency of 77.76 MHz then the phase offset equation simplifies to OFFSET[15:0] * 6.279 ps. If, however, the DPLL is locked to a reference whose frequency is +1 ppm from ideal, for example, then the actual internal clock period is 1 ppm shorter and the phase offset is 1 ppm smaller. When the OFFSET field is written, the phase of the output clocks is automatically ramped to the new offset value to avoid loss of synchronization. To adjust the phase offset without changing the phase of the output clocks, use the recalibration process enabled by FSCR3:RECAL. The OFFSET field is ignored when phase build-out is enabled (PBOEN=1 in the MCR10 register) and when the DPLL is not locked. See section 7.7.8. OFFSET2 Phase Offset Register 2 71h Bit 6 0 Bit 5 0 Bit 4 Bit 3 OFFSET[15:8] 0 0 Bit 2 0 Bit 1 0 Bit 0 0
Register Name: Register Description: Register Address: Bit 7 Name Default 0
Bits 7 to 0: Phase Offset (OFFSET[15:8]). See the OFFSET1 register description.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 Bit 6 -0 PBOFF Phase Build-Out Offset Register 72h Bit 5 0 Bit 4 0 Bit 3 Bit 2 PBOFF[5:0] 0 0 Bit 1 0
DS3105
Bit 0 0
Name Default
Bits 5 to 0: Phase Build-Out Offset Register (PBOFF[5:0]). An uncertainty of up to 5 ns is introduced each time a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The PBOFF field specifies a fixed offset for each phase build-out event to skew the average error toward zero. This field is a 2's complement signed integer. The offset in nanoseconds is PBOFF[5:0] * 0.101. Values greater than 1.4 ns or less than -1.4 ns may cause internal math errors and should not be used. See section 7.7.7.2.
Register Name: Register Description: Register Address: Bit 7 FLEN 1
PHLIM1 Phase Limit Register 1 73h Bit 6 NALOL 0 Bit 5 1 1 Bit 4 -0 Bit 3 -0 Bit 2 0 Bit 1 FINELIM[2:0] 1 Bit 0 0
Name Default
Bit 7: Fine Phase Limit Enable (FLEN). This configuration bit enables the fine phase limit specified in the FINELIM[2:0] field. The fine limit must be disabled for multi-UI jitter tolerance (see PHLIM2 fields). This field controls both T0 and T4. See section 7.7.6. 0 = Disabled 1 = Enabled Bit 6: No-Activity Loss of Lock (NALOL). The T0 and the T4 DPLLs can detect that an input clock has no activity very quickly (within two clock cycles). When NALOL=0, loss-of-lock is not declared when clock cycles are missing, and nearest edge locking (180) is used when the clock recovers. This gives tolerance to missing cycles. When NALOL=1, loss-of-lock is indicated as soon as no activity is detected, and the device switches to phase/frequency locking (360). This field controls both T0 and T4. See sections 7.5.3 and 7.7.6. 0 = No activity does not trigger loss-of-lock 1 = No activity does trigger loss-of-lock Bit 5: Leave set to 1 (test control). Bits 2 to 0: Fine Phase Limit (FINELIM[2:0]). This field specifies the fine phase limit window, outside of which loss-of-lock is declared. The FLEN bit enables this feature. The phase of the input clock has to be inside the fine limit window for two seconds before phase lock is declared. Loss-of-lock is declared immediately if the phase of the input clock is outside the phase limit window. The default value of 010 is appropriate for most situations. This field controls both T0 and T4. See section 7.7.6. 000 = Always indicates loss of phase lock--do not use 001 = Small phase limit window, 45 to 90 010 = Normal phase limit window, 90 to 180 (default) 100, 101, 110, 111 = Proportionately larger phase limit window
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 CLEN 1 PHLIM2 Phase Limit Register 2 74h Bit 6 MCPDEN 0 Bit 5 USEMCPD 0 Bit 4 -0 Bit 3 0 Bit 2 Bit 1 COARSELIM[3:0] 1 0
DS3105
Bit 0 1
Name Default
Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified in the COARSELIM[3:0] field. This field controls both T0 and T4. See section 7.7.6. 0 = Disabled 1 = Enabled Bit 6: Multi-Cycle Phase Detector Enable (MCPDEN). This configuration bit enables the multi-cycle phase detector and allows the DPLL to tolerate large-amplitude jitter and wander. The range of this phase detector is the same as the coarse phase limit specified in the COARSELIM[3:0] field. This field controls both T0 and T4. See section 7.7.5. 0 = Disabled 1 = Enabled Bit 5: Use Multi-Cycle Phase Detector in the DPLL Algorithm (USEMCPD). This configuration bit enables the DPLL algorithm to use the multi-cycle phase detector so that a large phase measurement drives faster DPLL pullin. When USEMCPD=0, phase measurement is limited to 360, giving slower pull-in at higher frequencies but with less overshoot. When USEMCPD=1, phase measurement is set as specified in the COARSELIM[3:0] field, giving faster pull-in. MCPDEN should be set to 1 when USEMCPD=1. This field controls both T0 and T4. See section 7.7.5. 0 = Disabled 1 = Enabled Bits 3 to 0: Coarse Phase Limit (COARSELIM[3:0]). This field specifies the coarse phase limit and the tracking range of the multi-cycle phase detector. The CLEN bit enables this feature. If jitter tolerance greater than 0.5 UI is required and the input clock is a high frequency signal then the DPLL can be configured to track phase errors over many UI using the multi-cycle phase detector. This field controls both T0 and T4. See section 7.7.5 and 7.7.6. 0000 = 1 UI 0001 = 3 UI 0010 = 7 UI 0011 = 15 UI 0100 = 31 UI 0101 = 63 UI 0110 = 127 UI 0111 = 255 UI 1000 = 511 UI 1001 = 1023 UI 1010 = 2047 UI 1011 = 4095 UI 1100 to 1111 = 8191 UI
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 NW 0 Bit 6 -0 PHMON Phase Monitor Register 76h Bit 5 -0 Bit 4 -0 Bit 3 0 Bit 2 -1 1 Bit 1
DS3105
Bit 0 0
Name Default
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2 kHz, 4 kHz or 8 kHz input clocks, this configuration bit enables a 5% tolerance noise window centered around the expected clock edge location. Noiseinduced edges outside this window are ignored, reducing the possibility of phase hits on the output clocks. This only applies to the T0 DPLL and should be enabled only when the T0 DPLL is locked to an input and the 180 phase detector is being used. 0 = All edges are recognized by the T0 DPLL 1 = Only edges within the 5% tolerance window are recognized by the T0 DPLL
Register Name: Register Description: Register Address: Bit 7 Name Default 0 Bit 6 0
PHASE1 Phase Register 1 77h Bit 5 0 Bit 4 Bit 3 PHASE[7:0] 0 0 Bit 2 0 Bit 1 0 Bit 0 0
The PHASE1 and PHASE2 registers must be read consecutively. See section 8.3. Bits 7 to 0: Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the PHASE2 register. PHASE is a 2's-complement signed integer that indicates the current value of the phase detector. The value is the output of the phase averager. When T4T0=0 in the MCR11 register, PHASE indicates the current phase of the T0 DPLL. When T4T0=1, PHASE indicates the current phase of the T4 DPLL. The averaged phase difference in degrees is equal to PHASE * 0.707. See section 7.7.10.
Register Name: Register Description: Register Address: Bit 7 Name Default 0
PHASE2 Phase Register 2 78h Bit 6 0 Bit 5 0 Bit 4 Bit 3 PHASE[15:8] 0 0 Bit 2 0 Bit 1 0 Bit 0 0
Bits 7 to 0: Current DPLL Phase (PHASE[15:8]). See the PHASE1 register description.
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: PHLKTO Phase Lock Timeout Register 79h Bit 5 1 Bit 4 1 Bit 3 Bit 2 PHLKTO[5:0] 0 0 Bit 1 1
DS3105
Name Default
Bit 7 Bit 6 PHLKTOM[1:0] 0 0
Bit 0 0
Bits 7 to 6: Phase Lock Timeout Multiplier (PHLKTOM[1:0]). This field is an unsigned integer that specifies the resolution of the phase lock timeout field PHLKTO[5:0]. 00 = 2 seconds 01 = 4 seconds 10 = 8 seconds 11 = 16 seconds Bits 5 to 0: Phase Lock Timeout (PHLKTO[5:0]). This field is an unsigned integer that, together with the PHLKTOM[1:0] field, specifies the length of time that the T0 DPLL attempts to lock to an input clock before declaring a phase lock alarm (by setting the corresponding LOCK bit in the ISR registers). The timeout period in seconds is PHLKTO[5:0] * 2^(PHLKTOM[1:0]+1). The state machine remains in the Pre-locked, Pre-locked 2 or Phase-lost modes for the specified time before declaring a phase alarm on the selected input. See section 7.7.1. FSCR1 Frame Sync Configuration Register 1 7Ah Bit 6 0 Bit 5 SYNCSRC[2:0] 0 Bit 4 0 Bit 3 8KINV 0 Bit 2 8KPUL 0 Bit 1 2KINV 0 Bit 0 2KPUL 0
Register Name: Register Description: Register Address: Bit 7 -0
Name Default
Bit 6 to 4: SYNC12 Source (SYNCSRC). This field determines whether the SYNC1 and SYNC2 pins are associated with the selected input clock or forced to be associated with a specific input clock. See section 7.9.7. 0XX = SYNC1 pins associated with T0 DPLL selected reference IC3 or IC5, SYNC2 pin associated with T0 DPLL selected reference IC4 or IC6 1X0 = SYNC1 pin associated with IC3, SYNC2 pin associated with IC4 1X1 = SYNC1 pin associated with IC5, SYNC2 pin associated with IC6 Bit 3: 8 kHz Invert (8KINV). When this bit is set to 1 the 8 kHz signal on clock output FSYNC is inverted. See section 7.8.2.5. 0 = FSYNC not inverted 1 = FSYNC inverted Bit 2: 8 kHz Pulse (8KPUL). When this bit is set to 1, the 8 kHz signal on clock output FSYNC is pulsed rather than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the clock period of OC3. See section 7.8.2.5. 0 = FSYNC not pulsed; 50% duty cycle 1 = FSYNC pulsed, with pulse width equal to OC3 period Bit 1: 2 kHz Invert (2KINV). When this bit is set to 1 the 2 kHz signal on clock output MFSYNC is inverted. See section 7.8.2.5. 0 = MFSYNC not inverted 1 = MFSYNC inverted Bit 0: 2 kHz Pulse (2KPUL). When this bit is set to 1, the 2 kHz signal on clock output MFSYNC is pulsed rather than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of MFSYNC is equal to the clock period of OC3. See section 7.8.2.5. 0 = MFSYNC not pulsed; 50% duty cycle 1 = MFSYNC pulsed, with pulse width equal to OC3 period
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 INDEP 0 FSCR2 Frame Sync Configuration Register 2 7Bh Bit 6 OCN 0 Bit 5 Bit 4 PHASE3[1:0] 0 0 Bit 3 Bit 2 PHASE2[1:0] 0 0
DS3105
Name Default
Bit 1 Bit 0 PHASE1[1:0] 0 0
Bit 7: Independent Frame Sync and Multi-frame Sync (INDEP). When this bit is set to 0, the 8 kHz frame sync on FSYNC and the 2 kHz multi-frame sync on MFSYNC are aligned with the other output clocks when synchronized with the SYNCn input. When this bit is 1, the frame sync and multi-frame sync are independent of the other output clocks, and their edge position may change without disturbing the other output clocks. See section 7.9.5. 0 = FSYNC and MFSYNC are aligned with other output clocks; all are synchronized by the SYNCn input 1 = FSYNC and MFSYNC are independent of the other clock outputs; only FSYNC and MFSYNC are synchronized by the SYNCn input Bit 6: Sync OC-N Rates (OCN). See section 7.9.2. 0 = SYNCn is sampled with a 6.48 MHz resolution; the selected reference must be 6.48 MHz 1 = If the selected reference is 19.44 MHz, SYNCn is sampled at 19.44 MHz and output alignment is to 19.44 MHz. If the selected reference is 38.88 MHz, SYNCn is sampled at 38.88 MHz. The selected reference must be either 19.44 MHz or 38.88 MHz Bits 5 to 4: External Sync Sampling Phase 3. (PHASE3[1:0]). This field adjusts the sampling of the SYNC3 input pin. Normally the falling edge of SYNC3 is aligned with the falling edge of the selected reference. All UI numbers listed below are UI of the sampling clock. See section 7.9.1. 00 = Coincident 01 = 0.5 UI early 10 = 1 UI late 11 = 0.5 UI late Bits 3 to 2: External Sync Sampling Phase 2. (PHASE2[1:0]). This field adjusts the sampling of the SYNC2 input pin. Normally the falling edge of SYNC2 is aligned with the falling edge of the selected reference. All UI numbers listed below are UI of the sampling clock. See section 7.9.1. 00 = Coincident 01 = 0.5 UI early 10 = 1 UI late 11 = 0.5 UI late Bits 1 to 0: External Sync Sampling Phase 1. (PHASE1[1:0]). This field adjusts the sampling of the SYNC1 input pin. Normally the falling edge of SYNC1 is aligned with the falling edge of the selected reference. All UI numbers listed below are UI of the sampling clock. See section 7.9.1. 00 = Coincident 01 = 0.5 UI early 10 = 1 UI late 11 = 0.5 UI late
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 RECAL 0 FSCR3 Frame Sync Configuration Register 3 7Ch Bit 6 0 Bit 5 MONLIM[2:0] 1 Bit 4 0 Bit 3 1 Bit 2 Bit 1 SOURCE[3:0] 1 1
DS3105
Bit 0 1
Name Default
Bit 7: Phase Offset Recalibration (RECAL). When set to 1 this configuration bit causes a recalibration of the phase offset between the output clocks and the selected reference. This process puts the DPLL into mini holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the OFFSET registers, and then switches the DPLL out of mini holdover. Unlike simply writing the OFFSET registers, the RECAL process causes no change in the phase offset of the output clocks. RECAL is automatically reset to 0 when recalibration is complete. See section 7.7.8. 0 = Normal operation 1 = Phase offset recalibration Bits 6 to 4: Sync Monitor Limit (MONLIM[2:0]). This field configures the sync monitor limit. When the external frame sync input is misaligned with respect to the MFSYNC output by the specified number of resampling clock cycles then a frame sync monitor alarm is declared in the FSMON bit of the OPSTATE register. See section 7.9.6. 000 = 1 UI 001 = 2 UI 010 = 3 UI 011 = 4 UI 100 = 5 UI 101 = 6 UI 110 = 7 UI 111 = 8 UI Bits 3 to 0: Sync Reference Source (SOURCE[3:0]). There are two modes of external frame sync operation, a mode using a single input pin (SYNC1) and a mode using three input pins (SYNC1, SYNC2, and SYNC3). When SOURCE = 11XX one of The SYNC1, SYNC2, and SYNC3 pins are selected as the external sync reference depending on which input clock is selected for T0. See section 7.9. When SOURCE != 11XX and automatic external frame sync is enabled (AEFSEN=1 in the MCR3 register), the external sync reference on the SYNC1 pin is enabled when the T0 DPLL is locked to the input clock specified by the SOURCE field. See section 7.9. 0000 to 0010 = {unused value, undefined} 0011 = IC3 0100 = IC4 0101 = IC5 0110 = IC6 0111to 1000 = {unused value, undefined} 1001 = IC9 1010 to 1011 = {unused value, undefined} 1011 = SYNC1,2,3 mode 11XX = SYNC1, SYNC2 and SYNC3 enabled
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Preliminary. Subject to Change Without Notice. Register Name: Register Description: Register Address: Bit 7 -0 INTCR Interrupt Configuration Register 7Dh Bit 6 -0 Bit 5 -0 Bit 4 -0 Bit 3 LOS 0 Bit 2 GPO 0 Bit 1 OD 1
DS3105
Name Default
Bit 0 POL 0
Bit 3: INTREQ Pin Mode (LOS). When GPO=0 this bit selects the function of the INTREQ pin. 0 = The INTREQ/LOS pin indicates interrupt requests 1 = The INTREQ/LOS pin indicates the real-time state of the selected reference activity monitor (see section 7.5.3). This function is most useful when external switching mode (section 7.6.5) is enabled (MCR10:EXTSW=1). Bit 2: INTREQ Pin General Purpose Output Enable (GPO). When set to 1 this bit configures the interrupt request pin to be a general purpose output whose value is set by the POL bit. 0 = INTREQ is function determined by the LOS bit 1 = INTREQ is a general purpose output Bit 1: INTREQ Pin Open Drain Enable (OD). When GPO = 0: 0 = INTREQ is driven in both inactive and active states 1 = INTREQ is driven high or low in the active state but is high impedance in the inactive state When GPO = 1: 0 = INTREQ is driven as specified by POL 1 = INTREQ is high impedance and POL has no effect Bit 0: INTREQ Pin Polarity (POL). When GPO = 0: 0 = INTREQ goes low to signal an interrupt request or LOS (active low) 1 = INTREQ goes high to signal interrupt request or LOS (active high) When GPO = 1: 0 = INTREQ driven low 1 = INTREQ driven high
Register Name: Register Description: Register Address: Bit 7 Name Default 1
PROT Protection Register 7Eh Bit 6 0 Bit 5 0 Bit 4 Bit 3 PROT[7:0] 0 0 Bit 2 1 Bit 1 0 Bit 0 1
Bits 7 to 0: Protection Control (PROT[7:0]). This field can be used to protect the rest of the register set from inadvertent writes. In protected mode writes to all other registers are ignored. In single unprotected mode, one register (other than PROT) can be written, but after that write the device reverts to protected mode (and the value of PROT is internally changed to 00h). In fully unprotected mode all register can be written without limitation. See section 7.2. 1000 0101 = Fully unprotected mode 1000 0110 = Single unprotected mode all other values = Protected mode
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9
9.1
JTAG TEST ACCESS PORT AND BOUNDARY SCAN
JTAG Description
The DS3105 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. Figure 9-1 shows a block diagram. The DS3105 contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register
The TAP has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS. Details on these pins can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.11990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 9-1. JTAG Block Diagram
BOUNDARY SCAN REGISTER DEVICE IDENTIFICATION REGISTER BYPASS REGISTER
INSTRUCTION REGISTER
SELECT
TEST ACCESS PORT CONTROLLER
TRI-STATE
10k JTDI
10k JTMS JTCLK
10k JTRST JTDO
9.2
JTAG TAP Controller State Machine Description
This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in Figure 9-2 are described in the following paragraphs. Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The instruction register contains the IDCODE instruction. All system logic on the device operates normally. Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction register and all test registers remain idle. Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the SelectIR-SCAN state. Capture-DR. Data can be parallel-loaded into the test register selected by the current instruction. If the instruction does not call for a parallel load or the selected test register does not allow parallel loads, the register remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or to the Exit1DR state if JTMS is high.
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MUX
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Shift-DR. The test register selected by the current instruction is connected between JTDI and JTDO and data is shifted one stage toward the serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it maintains its previous state. Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state, which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR state. Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on JTCLK with JTMS high puts the controller in the Exit2-DR state. Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR state. Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output because of changes in the shift register. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state. Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller enters the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state. Shift-IR. In this state, the instruction register's shift register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK toward the serial output. The parallel register and the test registers remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state, while moving data one stage through the instruction shift register. Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process. Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge on JTCLK. Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The controller loops back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state. Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS low puts the controller in the Run-Test-Idle state. With JTMS high, the controller enters the Select-DR-Scan state.
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Figure 9-2. JTAG TAP Controller State Machine
Test-Logic-Reset 1 0 1 Select DR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1- DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 1 0 1 1 1 Select IR-Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 1 1
0
Run-Test/Idle
0
0
0
0
9.3
JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the UpdateIR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction parallel output. Table 9-1 shows the instructions supported by the DS3105 and their respective operational binary codes.
Table 9-1. JTAG Instruction Codes
INSTRUCTIONS SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001
SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. First, the digital I/Os of the device can be sampled at the boundary scan register, using the Capture-DR state, without interfering with the device's normal operation. Second, data can be shifted into the boundary scan register through JTDI using the Shift-DR state.
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EXTEST. EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur: (1) Once the EXTEST instruction is enabled through the Update-IR state, the parallel outputs of the digital output pins are driven. (2) The boundary scan register is connected between JTDI and JTDO. (3) The Capture-DR state samples all digital inputs into the boundary scan register. BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI is connected to JTDO through the 1-bit bypass register. This allows data to pass from JTDI to JTDO without affecting the device's normal operation. IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the device identification register is selected. The device ID code is loaded into the device identification register on the rising edge of JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shift the ID code out serially through JTDO. During Test-Logic-Reset, the ID code is forced into the instruction register's parallel output. HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI and JTDO. CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
9.4
JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers--the bypass register and the boundary scan register. An optional test register, the identification register, has been included in the device design. It is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller. Bypass Register. This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions to provide a short path between JTDI and JTDO. Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells and digital I/O cells. BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm. Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device identification code for the DS3105 is shown in Table 9-2.
Table 9-2. JTAG ID Code
DEVICE DS3105 REVISION Consult factory DEVICE CODE 0000000010100011 MANUFACTURER CODE 00010100001 REQUIRED 1
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10
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin with Respect to VSS (except VDD)......................................................-0.3V to +5.5V Supply Voltage Range (VDD) with Respect to VSS...................................................................-0.3V to +1.98V Supply Voltage Range (VDDIO) with Respect to VSS.................................................................-0.3V to +3.63V Ambient Operating Temperature Range...............................................................................-40C to +85C Junction Operating Temperature Range.............................................................................-40C to +125C Storage Temperature Range............................................................................................-55C to +125C Soldering Temperature..................................................................See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. Ambient operating temperature range when device is mounted on a four-layer JEDEC test board with no airflow. Note: The typical values listed in the tables of section 10 are not production tested.
10.1
DC Characteristics
SYMBOL VDD VDDIO TA TJ CONDITIONS MIN 1.62 3.135 -40 -40 TYP 1.8 3.3 MAX 1.98 3.465 +85 +125 UNITS V V C C
Table 10-1. Recommended DC Operating Conditions
PARAMETER Supply Voltage, Core Supply Voltage, I/O Ambient Temperature Range Junction Temperature Range
Table 10-2. DC Characteristics
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) PARAMETER SYMBOL CONDITIONS Supply Current, Core Supply Current, I/O Supply Current from VDD_OC6 When Output OC6 Enabled Input Capacitance Output Capacitance
Note 1: Note 2: Note 3:
MIN
TYP TBD TBD 16 5 7
MAX TBD TBD
UNITS mA mA mA pF pF
IDD IDDIO IDDOC6 CIN COUT
Note 1, 2 Note 1, 2 Note 3
12.800 MHz clock applied to REFCLK and 19.44 MHz clock applied to one CMOS/TTL input clock pin. Output clock pin OC3 at 19.44 MHz driving 100 pF load; all other inputs at VDDIO or grounded; all other outputs disabled and open. TYP current measured at VDD=1.8V and VDDIO=3.3V, MAX current measured at VDD=1.98V and VDDIO=3.465V 19.44MHz output clock frequency, driving the load shown in Figure 10-1.
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Table 10-3. CMOS/TTL Pins
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input Leakage Input Leakage, pins with internal pullup resistor (50k typical) Input Leakage, pins with internal pulldown resistor (50k typical) Output Leakage (when High-Z) Output High Voltage (IO = -4.0mA) Output High Voltage (IO = -4.0mA) Output Low Voltage (IO = +4.0mA)
Note 1: Note 2:
MIN 2.0 -0.3 -10 -85 -10 -10 2.4 2.0 0
TYP
MAX 5.5 +0.8 +10 +10 +85 +10 VDDIO VDDIOB 0.4
UNITS V V A A A A V V V
IIL IILPU IILPD ILO VOH VOH VOL
Note 1 Note 1 Note 1 Note 1 Note 2
0V < VIN < VDDIO for all other digital inputs. For OC1B through OC5B when VDDIOB=2.5V.
Table 10-4. LVDS/LVPECL Input Pins
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) PARAMETER SYMBOL CONDITIONS Input Voltage Tolerance VTOL Note 1 Input Voltage Range Input Differential Voltage Input Differential Logic Threshold
Note 1:
MIN 0 0 0.1 -100
TYP
MAX VDDIO 2.4 1.4 +100
UNITS V V V mV
VIN VID VIDTH
VID=100 mV
The device can tolerate this range of voltages w.r.t. VSS on its ICxPOS and ICxNEG pins without being damaged. Proper operation of the differential input circuitry is only guaranteed when the other specifications in this table are met.
Table 10-5. LVDS Output Pins
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) PARAMETER SYMBOL CONDITIONS Output High Voltage VOHLVDS Note 1 Output Low Voltage VOLLVDS Note 1 Differential Output Voltage VODLVDS Output Offset (Common Mode) Voltage VOSLVDS 25C, Note 1 Difference in Magnitude of Output VDOSLVDS Differential Voltage for Complementary States
Note 1: Note 2:
MIN 0.9 247 1.125
TYP
MAX 1.6 454 1.375 25
350 1.25
UNITS V V mV V mV
With 100 load across the differential outputs. The differential outputs can easily be interfaced to LVDS, LVPECL and CML inputs on neighboring ICs using a few external passive components. See Maxim App Note HFAN-1.0 for details.
Table 10-6. LVPECL Level-Compatible Output Pins
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) PARAMETER SYMBOL CONDITIONS Differential Output Voltage VODPECL Output Offset (Common Mode) Voltage VOSPECL 25C, Note 1 Difference in Magnitude of Output VDOSPECL Differential Voltage for Complementary States
Note 1: Note 2:
MIN 595
TYP 700 0.8
MAX 930
UNITS mV V mV
50
With 100 load across the differential outputs. The differential outputs can easily be interfaced to LVDS, LVPECL and CML inputs on neighboring ICs using a few external passive components. See Maxim App Note HFAN-1.0 for details.
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Figure 10-1. Recommended Termination for LVDS Pins
50
50 100
(5%)
LVDS DRIVER
ICnPOS
OCnPOS
50
DS3105
iICnNEG OCnNEG
50
100
(5%)
LVDS RCVR
Figure 10-2. Recommended Termination for LVPECL Signals on Differential Input Pins
3.3V 130 50 130
LVPECL DRIVER
ICnPOS 50 ICnNEG
DS3105
82 GND
82
Figure 10-3 Recommended Termination for LVPECL Level-Compatible Output Pins
3.3V 82 OCnPOS 50 50 .01 uF 82
DS3105
OCnNEG
PECL RCVR
130 GND 130
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10.2 Input Clock Timing
Table 10-7. Input Clock Timing
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) PARAMETER SYMBOL MIN Input Clock Period, 8ns (125MHz) tCYC CMOS/TTL Input Pins Input Clock Period, 6.4ns (156.25MHz) tCYC LVDS/LVPECL Input Pins 3ns or 30% of tCYC, Input Clock High, Low Time t H, t L whichever is smaller TYP MAX 500s (2kHz) 500s (2kHz)
10.3 Output Clock Timing
Table 10-8. Input Clock to Output Clock Delay
INPUT FREQUENCY 8 kHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz OUTPUT FREQUENCY 8 kHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz DELAY, INPUT CLOCK EDGE TO OUTPUT CLOCK EDGE 0.0 1.5ns -12 1.5ns 0.0 1.5ns 0.0 1.5ns 0.0 1.5ns 0.0 1.5ns 0.0 1.5ns 0.0 1.5ns
Table 10-9. Output Clock Phase Alignment, Frame Sync Alignment Mode
OUTPUT FREQUENCY 8 kHz (FSYNC) 2 kHz 8 kHz 1.544 MHz 2.048 MHz 44.736 MHz 34.368 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 311.04 MHz DELAY, MFSYNC FALLING EDGE TO OUTPUT CLOCK FALLING EDGE 0.0 0.5ns 0.0 0.5ns 0.0 0.5ns 0.0 1.25ns 0.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns -2.0 1.25ns
See section 7.9 for details on frame sync alignment and the SYNC1,2,3 pins.
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10.4 SPI Interface Timing
Table 10-10. SPI Interface Timing
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) (Figure 10-4) PARAMETER (Note 1) SYMBOL SCLK Frequency fBUS SCLK Cycle Time tCYC tSUC CS Setup to First SCLK Edge tHDC CS Hold time After Last SCLK Edge SCLK High Time tCLKH SCLK Low Time tCLKL SDI Data Setup Time tSUI SDI Data Hold Time tHDI SDO Enable Time (High-Impedance to Output Active) tEN SDO Disable Time (Output Active to High-Impedance) tDIS SDO Data Valid Time tDV SDO Data Hold Time After Update SCLK Edge tHDO
Note 1:
MIN 100 15 15 50 50 5 15 0
TYP
MAX 6
25 50 5
UNITS MHz ns ns ns ns ns ns ns ns ns ns ns
All timing is specified with 100 pF load on all SPI pins.
Figure 10-4. SPI Interface Timing Diagram
CPHA = 0
CS
tSUC SCLK tCLKH tCYC tCLKL tHDC
tSUI SDI SDO
tHDI tDV tDIS
tEN
tHDO
CPHA = 1
CS
tSUC SCLK tCLKH tCYC tCLKL tHDC
tSUI SDI SDO
tHDI tDV tDIS
tEN
tHDO
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10.5 JTAG Interface Timing
Table 10-11. JTAG Interface Timing
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) (Figure 10-5) PARAMETER SYMBOL MIN JTCLK Clock Period t1 JTCLK Clock High/Low Time (Note 1) t2/t3 50 JTCLK to JTDI, JTMS Setup Time t4 50 JTCLK to JTDI, JTMS Hold Time t5 50 JTCLK to JTDO Delay t6 2 JTCLK to JTDO High-Z Delay (Note 2) t7 2 t8 100 JTRST Width Low Time
Note 1: Note 2:
TYP 1000 500
MAX
50 50
UNITS ns ns ns ns ns ns ns
Clock can be stopped high or low. Not tested during production test.
Figure 10-5. JTAG Timing Diagram
t1 t2 JTCLK t3
t4
t5
JTDI, JTMS, JTRST t6 t7
JTDO
JTRST
t8
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10.6 Reset Pin Timing
Table 10-12. Reset Pin Timing
(VDD = 1.8V 10%; VDDIO = 3.3V 5%, TA = -40C to +85C) (Figure 10-6) PARAMETER SYMBOL t1 RST low time (Note 1) t2 SONSDH, SRCSW, O3F[2:0], O6F[2:0] setup time to RST t3 SONSDH, SRCSW, O3F[2:0], O6F[2:0] hold time from RST MIN 1000 0 50 TYP MAX UNITS ns ns ns
Note 1: RST should be held low while the REFCLK oscillator stabilizes. It is recommended to force RST low during power up. The 1000 ns minimum time applies if the RST pulse is applied any time after the device has powered up and the oscillator has stabilized.
Figure 10-6. Reset Pin Timing Diagram
t1 RST* t2 t3 SONSDH OxF[2:0] SRCSW X valid X
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11 PIN ASSIGNMENTS
Table 11-1 below lists pin assignments sorted in alphabetical order by pin name. Figure 11-1 show pin assignments arranged by pin number.
Table 11-1. Pin Assignments Sorted by Signal Name
PIN NAME AVDD_DL AVDD_PLL1 AVDD_PLL2 AVDD_PLL3 AVDD_PLL4 AVSS_DL AVSS_PLL1 AVSS_PLL2 AVSS_PLL3 AVSS_PLL4 CPHA CS FSYNC IC3 IC4 IC5NEG IC5POS IC6NEG IC6POS IC9 INTREQ / LOS JTCLK JTDI JTDO JTMS JTRST PIN NUMBER 59 4 7 9 11 55 3 8 10 12 42 44 17 29 30 24 23 26 25 34 5 49 51 50 41 37 PIN NAME MFSYNC O3F1 / SRFAIL O3F2 / LOCK O6F0 / GPIO1 O6F1 / GPIO2 O6F2 / GPIO3 OC3 OC6NEG OC6POS REFCLK RST SCLK SDI SDO SONSDH / GPIO4 SRCSW SYNC1 SYNC2 SYNC3 / O3F0 TEST VDD VDDIO VDD_OC6 VSS VSS_OC6 PIN NUMBER 18 38 36 45 46 63 56 19 20 6 48 47 43 52 64 13 28 33 35 2 27, 39, 57, 58 14, 32, 54, 61 22 1, 15, 16, 31, 40, 53, 60, 62 21
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Figure 11-1. Pin Assignment Diagram
SONSDH/GPIO4 O6F2/GPIO3 VSS VDDIO VSS AVDD_DL VDD VDD OC3 AVSS_DL VDDIO VSS SDO JTDI JTDO JTCLK VSS TEST AVSS_PLL1 AVDD_PLL1 INTREQ/LOS REFCLK AVDD_PLL2 AVSS_PLL2 AVDD_PLL3 AVSS_PLL3 AVDD_PLL4 AVSS_PLL4 SRCSW VDDIO VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DS3105
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RST SCLK O6F1/GPIO2 O6F0/GPIO1 CS SDI CPHA JTMS VSS VDD O3F1/SRFAIL JTRST O3F2/LOCK SYNC3/O3F0 IC9 SYNC2
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FSYNC MFSYNC OC6POS OC6NEG VSS_OC6 VDD_OC6 IC5POS IC5NEG IC6POS IC6NEG VDD SYNC1 IC3 IC4 VSS VDDIO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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12 MECHANICAL INFORMATION
Figure 12-1. LQFP Mechanical Dimensions
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Table 12-1. LQFP Thermal Properties, Natural Convection
PARAMETER Ambient Temperature (Note 1) Junction Temperature Theta-JA (JA), Still Air (Note 2) Psi-JB Psi-JT MIN -40C -40C TYP -- -- TBD C/W TBD C/W TBD C/W MAX +85C +125C
Note 1: The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power. Note 2: Theta-JA (JA) is the junction to ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power.
Table 12-2. LQFP Theta-JA (JA) vs. Airflow
FORCED AIR (METERS PER SECOND) 0 1 2.5 THETA-JA (JA) TBD C/W TBD C/W TBD C/W
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13 ACRONYMS AND ABBREVIATIONS
AIS AMI APLL BITS BPV DFS DPLL ESF EXZ GbE I/O LOS LVDS LVPECL MTIE OCXO OOF PBO PFD PLL ppb ppm pk-pk rms RAI RO R/W SDH SEC SETS SF SONET SSM SSU STM TDEV TCXO UI UIpp XO alarm indication signal alternate mark inversion analog phase locked loop building integrated timing supply bipolar violation digital frequency synthesis digital phase locked loop extended superframe excessive zeros gigabit ethernet input/output loss of signal low voltage differential signal low voltage positive emitter-coupled logic Maximum Time Interval Error oven controlled crystal oscillator out of frame alignment phase build-out phase/frequency detector phase locked loop parts per billion parts per million peak-to-peak root-mean-square remote alarm indication read-only read/write synchronous digital hierarchy SDH equipment clock synchronous equipment timing source superframe synchronous Optical Network synchronization status message synchronization supply unit synchronous Transport Module time deviation temperature compensated crystal oscillator unit interval unit interval, peak to peak crystal oscillator
TRADEMARK ACKNOWLEDGEMENTS
Motorola is a registered trademark of Motorola, Inc. Semtech and Semtech Corp. are registered trademarks of Semtech Corporation. SPI is a trademark of Motorola, Inc. Telcordia is a registered trademark of Telcordia Technologies
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14 DATA SHEET REVISION HISTORY
REVISION 02/28/07 3/1/07 DESCRIPTION First version released to customers. In the ICR register description, updated the FREQ field description explicitly mention its use in LOCK8K mode and to indicate that 31.25 MHz is not a valid setting for LOCK8K mode. Updated section 7.4 to indicate minimum high time or low time is 3ns or 30% of clock period, whichever is smaller. In Table 7-1 added indications that IC5 and IC6 can be configured as CMOS/TTL inputs. In section 7.8.1 added hyperlink to Maxim app note HFAN-1.0. Added Note 2 to Table 10-5. Added Note 2 to Table 10-6. Updated Table 10-7 to clarify minimum high time and low time (and therefore duty cycle) for input clocks. Deleted VHYST spec from Table 10-4 and deleted reference to IEEE1596.3 standard from Table 1-1. Added section 7.13. Deleted mention of slave mode from MCR9:AUTOBW bit description. In the OPSTATE register description, changed the default value of T4LOCK to 0. 4/4/07 In the MCR4 register description, deleted the T4DIGFB bit description and changed the default value for bit 6 to 0. Edited section 7.7.6 and the DLIMIT1 and DLIMIT3:FLLOL descriptions to indicate that the T4 DPLL's hard limit is fixed at 80ppm and is not controlled by the HARDLIM field. In Table 10-6 deleted VOHPECL and VOLPECL specs and changed VOSPECL spec to 0.8V typical. 4/17/07 Added information about custom clock rates to page 1 bullets and section 5 bullets, and added a new section 7.8.2.6. Changed caption for Table 7-14 from "Possible Frequencies" to "Standard Frequencies". In section 7.5.3, second paragraph, first sentence, deleted "frequency range error" as a criteria for entering mini holdover. 4/30/07 Changed pin name INTREQ/SRFAIL to INTREQ/LOS and changed register bit INTCR:SRFAIL to LOS. This affected the pin description in Table 6-3, the name of INTCR bit 3 in Table 8-1, the MSR2:SRFAIL register description, and the bit descriptions for INTCR. Edited T4BW register to not have bit 2. Updated the data sheet in several places to indicate CMOS/TTL input clock pins can accept any multiple of 2kHz up to 125MHz and that differential inputs clock pins can accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25MHz. In Table 7-9, added frequencies 45.824, 22.912, 29.824 and 14.912 MHz. In the T0LBW register definition, changed the default value to 00h. In the T0ABW register definition, changed the default value to 01h. Updated page 1 feature bullet, section 5 feature bullet and section 7.8.2.6 text to indicate maximum custom frequency is 311.04MHz. 5/18/07 In Figure 7-1, changed OC10 to FSYNC, OC11 to MFSYNC, OCnEN to FSEN and MFSEN, OCnINV to 8KINV and 2KINV, and OCnPOL to 8KPOL and 2KPOL. In Table 10-3, changed max from VDD to VDDIO and added separate VOH spec for OC1B through OC5B when VDDIOB is 2.5V. In Table 10-10, changed tDV max to 50ns.
3/5/07
3/9/07 4/3/07
5/10/07
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06/04/07
In Table 6-6, changed which AVDD_PLLx and AVSS_PLLx goes with which APLL to match how the device is actually arranged. Deleted one reference to the PMPBEN bit that was inadvertently copied over from the DS3100 data sheet. In Table 1-1, added references to G.82261 and G.8262 (pre-published). In sections 7.11 and 7.13, added notes to indicate that system software must wait at least 100s after reset is deasserted before initializing the device
06/15/07
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